Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	754825	0	0
entropy_period_rd_A	2147483647	2261	0	0
intr_enable_rd_A	2147483647	3208	0	0
prefix_0_rd_A	2147483647	2509	0	0
prefix_10_rd_A	2147483647	2428	0	0
prefix_1_rd_A	2147483647	2428	0	0
prefix_2_rd_A	2147483647	2411	0	0
prefix_3_rd_A	2147483647	2595	0	0
prefix_4_rd_A	2147483647	2427	0	0
prefix_5_rd_A	2147483647	2424	0	0
prefix_6_rd_A	2147483647	2412	0	0
prefix_7_rd_A	2147483647	2490	0	0
prefix_8_rd_A	2147483647	2385	0	0
prefix_9_rd_A	2147483647	2383	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	754825	0	0
T33	266435	42385	0	0
T38	2408	0	0	0
T45	0	59329	0	0
T51	0	74412	0	0
T52	0	13334	0	0
T57	84527	0	0	0
T86	0	52827	0	0
T87	0	98492	0	0
T130	0	34717	0	0
T131	0	122735	0	0
T132	0	143006	0	0
T133	0	33983	0	0
T134	146458	0	0	0
T135	55254	0	0	0
T136	41269	0	0	0
T137	5887	0	0	0
T138	127891	0	0	0
T139	218360	0	0	0
T140	3768	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2261	0	0
T52	143509	69	0	0
T90	5195	0	0	0
T93	0	185	0	0
T94	0	29	0	0
T96	0	10	0	0
T121	0	68	0	0
T123	0	154	0	0
T128	0	6	0	0
T152	0	8	0	0
T153	0	116	0	0
T154	0	11	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3208	0	0
T52	143509	91	0	0
T90	5195	0	0	0
T93	0	136	0	0
T94	0	44	0	0
T96	0	12	0	0
T121	0	92	0	0
T123	0	119	0	0
T124	0	24	0	0
T152	0	8	0	0
T153	0	109	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0
T163	0	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2509	0	0
T52	143509	58	0	0
T90	5195	0	0	0
T93	0	68	0	0
T94	0	45	0	0
T96	0	1	0	0
T121	0	47	0	0
T123	0	75	0	0
T128	0	5	0	0
T152	0	8	0	0
T153	0	120	0	0
T154	0	8	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T52	143509	42	0	0
T90	5195	0	0	0
T93	0	145	0	0
T94	0	35	0	0
T96	0	3	0	0
T120	0	42	0	0
T121	0	45	0	0
T123	0	99	0	0
T152	0	1	0	0
T153	0	127	0	0
T154	0	6	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T52	143509	49	0	0
T90	5195	0	0	0
T93	0	150	0	0
T94	0	36	0	0
T96	0	1	0	0
T121	0	40	0	0
T123	0	107	0	0
T128	0	3	0	0
T152	0	8	0	0
T153	0	109	0	0
T154	0	11	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2411	0	0
T52	143509	57	0	0
T90	5195	0	0	0
T93	0	72	0	0
T94	0	42	0	0
T120	0	39	0	0
T121	0	35	0	0
T123	0	89	0	0
T152	0	11	0	0
T153	0	144	0	0
T154	0	4	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0
T164	0	30	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2595	0	0
T52	143509	53	0	0
T90	5195	0	0	0
T93	0	133	0	0
T94	0	39	0	0
T96	0	9	0	0
T121	0	37	0	0
T123	0	100	0	0
T128	0	6	0	0
T152	0	8	0	0
T153	0	121	0	0
T154	0	7	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2427	0	0
T52	143509	31	0	0
T90	5195	0	0	0
T93	0	109	0	0
T94	0	36	0	0
T96	0	2	0	0
T121	0	45	0	0
T123	0	63	0	0
T128	0	4	0	0
T152	0	8	0	0
T153	0	143	0	0
T154	0	6	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T52	143509	44	0	0
T90	5195	0	0	0
T93	0	143	0	0
T94	0	34	0	0
T96	0	6	0	0
T121	0	32	0	0
T123	0	75	0	0
T128	0	6	0	0
T152	0	7	0	0
T153	0	65	0	0
T154	0	6	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2412	0	0
T52	143509	39	0	0
T90	5195	0	0	0
T93	0	106	0	0
T94	0	49	0	0
T96	0	6	0	0
T120	0	39	0	0
T121	0	32	0	0
T123	0	86	0	0
T152	0	9	0	0
T153	0	122	0	0
T154	0	6	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2490	0	0
T52	143509	36	0	0
T90	5195	0	0	0
T93	0	179	0	0
T94	0	28	0	0
T96	0	3	0	0
T121	0	53	0	0
T123	0	101	0	0
T128	0	6	0	0
T152	0	5	0	0
T153	0	120	0	0
T154	0	8	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T52	143509	54	0	0
T90	5195	0	0	0
T93	0	132	0	0
T94	0	30	0	0
T96	0	11	0	0
T121	0	41	0	0
T123	0	83	0	0
T128	0	6	0	0
T152	0	6	0	0
T153	0	125	0	0
T154	0	5	0	0
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T156	1385	0	0	0
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T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2383	0	0
T52	143509	38	0	0
T90	5195	0	0	0
T93	0	132	0	0
T94	0	35	0	0
T96	0	6	0	0
T121	0	39	0	0
T123	0	81	0	0
T128	0	5	0	0
T152	0	10	0	0
T153	0	120	0	0
T154	0	8	0	0
T155	289355	0	0	0
T156	1385	0	0	0
T157	15321	0	0	0
T158	89251	0	0	0
T159	1508	0	0	0
T160	134027	0	0	0
T161	27502	0	0	0
T162	128493	0	0	0