Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100482491	1			T1	8192		T2	536		T3	19333
all_values[1]	100482491	1			T1	8192		T2	536		T3	19333
all_values[2]	100482491	1			T1	8192		T2	536		T3	19333

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

510920

1

T1

183

T3

208

T14

3

auto[1]

300936553

1

T1

24393

T2

1608

T3

57791

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299910954

1

T1

24336

T2

1377

T3

57477

auto[1]

1536519

1

T1

240

T2

231

T3

522

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	176962	1			T1	181		T3	206		T15	1
all_values[0]	auto[0]	auto[1]	2066	1			T1	2		T3	2		T15	2
all_values[0]	auto[1]	auto[0]	99793356	1			T1	7931		T2	459		T3	18953
all_values[0]	auto[1]	auto[1]	510107	1			T1	78		T2	77		T3	172
all_values[1]	auto[0]	auto[0]	154243	1			T14	2		T19	16		T4	21
all_values[1]	auto[0]	auto[1]	1460	1			T14	1		T19	2		T40	2
all_values[1]	auto[1]	auto[0]	99816075	1			T1	8112		T2	459		T3	19159
all_values[1]	auto[1]	auto[1]	510713	1			T1	80		T2	77		T3	174
all_values[2]	auto[0]	auto[0]	174573	1			T16	5		T17	207		T4	21
all_values[2]	auto[0]	auto[1]	1616	1			T16	1		T17	1		T98	1
all_values[2]	auto[1]	auto[0]	99795745	1			T1	8112		T2	459		T3	19159
all_values[2]	auto[1]	auto[1]	510557	1			T1	80		T2	77		T3	174