Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.25 96.16 92.75 66.52 62.88 93.39 99.79


Total modules in report: 54
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tlul_err_resp 57.14 71.43 50.00 50.00
keccak_round 74.39 65.98 100.00 26.67 79.31 100.00
kmac_app 80.04 90.99 84.93 37.78 86.52 100.00
keccak_2share 81.25 100.00 75.00 50.00 100.00
kmac_staterd 90.00 100.00 70.00 100.00
prim_intr_hw 90.35 95.00 76.39 90.00 100.00
prim_intr_hw 100.00 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) 91.67 100.00 75.00 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) 82.59 90.00 77.78 80.00
kmac 91.19 96.27 93.33 63.67 100.00 93.85 100.00
sha3 92.32 97.56 88.89 81.82 93.33 100.00
kmac_errchk 92.60 96.83 96.67 73.33 96.15 100.00
sha3pad 92.88 99.38 88.37 80.95 95.70 100.00
prim_fifo_sync 93.36 100.00 73.44 100.00 100.00
prim_fifo_sync 100.00 100.00
prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) 100.00 100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) 84.38 100.00 68.75
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) 100.00 100.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) 87.50 100.00 75.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=4 ) 100.00 100.00
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 ) 81.25 100.00 62.50
prim_fifo_sync ( parameter Width=72,Pass=1,Depth=10,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=4 ) 93.75 100.00 87.50
tlul_adapter_sram 93.82 98.56 80.56 96.15 100.00
tlul_adapter_sram 98.08 96.15 100.00
tlul_adapter_sram ( parameter SramAw=7,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) 90.96 98.59 83.33
tlul_adapter_sram ( parameter SramAw=9,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=1,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=32,DataBitWidth=2,WoffsetWidth=1,DataWidth=32 ) 88.15 98.53 77.78
kmac_core 94.46 98.55 92.86 100.00 92.00 88.89
prim_arbiter_fixed 95.05 87.50 92.68 100.00 100.00
prim_fifo_sync_cnt 95.33 96.00 90.00 100.00
prim_fifo_sync_cnt 100.00 100.00
prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 ) 86.00 92.00 80.00
prim_fifo_sync_cnt ( parameter Depth=10,Secure=0,PtrW=4,DepthW=4,WrapPtrW=5 ) 100.00 100.00 100.00
tlul_rsp_intg_gen 95.83 91.67 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 83.33 83.33
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_subreg_shadow 97.12 100.00 88.46 100.00 100.00
tlul_socket_1n 97.25 100.00 93.33 95.65 100.00
prim_packer 97.50 100.00 100.00 90.00 100.00
kmac_msgfifo 97.92 100.00 100.00 91.67 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
kmac_reg_top 99.87 100.00 99.46 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
prim_count 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
sha3pad_assert_if 100.00 100.00
prim_mubi4_sender 100.00 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 + DW=32,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_slicer 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=32,SwAccess=1,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) 100.00 100.00
kmac_csr_assert_fpv 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_sram_byte 100.00 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf
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