Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
366830 |
1 |
|
|
T1 |
164 |
|
T2 |
108 |
|
T3 |
2 |
auto[1] |
329288 |
1 |
|
|
T3 |
250 |
|
T17 |
246 |
|
T18 |
44 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174221 |
1 |
|
|
T1 |
51 |
|
T2 |
24 |
|
T3 |
56 |
lower_val |
172500 |
1 |
|
|
T1 |
38 |
|
T2 |
26 |
|
T3 |
70 |
zero_val |
1813 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348894 |
1 |
|
|
T1 |
86 |
|
T2 |
48 |
|
T3 |
130 |
lower_val |
347212 |
1 |
|
|
T1 |
78 |
|
T2 |
60 |
|
T3 |
122 |
zero_val |
12 |
1 |
|
|
T165 |
2 |
|
T166 |
2 |
|
T167 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46122 |
1 |
|
|
T1 |
31 |
|
T2 |
14 |
|
T14 |
60 |
higher_val |
higher_val |
auto[1] |
41362 |
1 |
|
|
T3 |
28 |
|
T17 |
50 |
|
T18 |
1 |
higher_val |
lower_val |
auto[0] |
45393 |
1 |
|
|
T1 |
20 |
|
T2 |
10 |
|
T14 |
76 |
higher_val |
lower_val |
auto[1] |
41341 |
1 |
|
|
T3 |
28 |
|
T17 |
30 |
|
T18 |
8 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T166 |
1 |
|
T168 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T169 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45620 |
1 |
|
|
T1 |
22 |
|
T2 |
11 |
|
T14 |
59 |
lower_val |
higher_val |
auto[1] |
41046 |
1 |
|
|
T3 |
37 |
|
T17 |
16 |
|
T18 |
3 |
lower_val |
lower_val |
auto[0] |
45361 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T14 |
65 |
lower_val |
lower_val |
auto[1] |
40472 |
1 |
|
|
T3 |
33 |
|
T17 |
23 |
|
T18 |
6 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T166 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
669 |
1 |
|
|
T3 |
1 |
|
T16 |
1 |
|
T18 |
1 |
zero_val |
higher_val |
auto[1] |
230 |
1 |
|
|
T67 |
2 |
|
T37 |
2 |
|
T170 |
1 |
zero_val |
lower_val |
auto[0] |
687 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
227 |
1 |
|
|
T17 |
2 |
|
T67 |
2 |
|
T37 |
2 |