Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
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Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
hash_mode 3 0 3 100.00 100 1 1 0
kmac_mode 2 0 2 100.00 100 1 1 2
msgfifo_depth 11 0 11 100.00 100 1 1 0
msgfifo_empty 2 0 2 100.00 100 1 1 2
msgfifo_full 2 0 2 100.00 100 1 1 2


Summary for Variable hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 11501712 1 T1 4129 T2 357 T3 15714
shake 55242500 1 T1 6598 T2 47 T3 3736
sha3 35442362 1 T1 6 T2 23 T3 903



Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 90683895 1 T1 6602 T2 70 T3 4638
auto[1] 11502679 1 T1 4131 T2 357 T3 15715



Summary for Variable msgfifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for msgfifo_depth

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
depth[0x00] 100638155 1 T1 10373 T2 240 T3 20353
depth[0x01] 999381 1 T1 249 T2 86 T16 11
depth[0x02] 178244 1 T1 52 T2 71 T16 9
depth[0x03] 145020 1 T1 44 T2 23 T16 8
depth[0x04] 92552 1 T1 14 T2 7 T16 7
depth[0x05] 55582 1 T1 1 T16 5 T17 6
depth[0x06] 19917 1 T19 60 T40 609 T41 199
depth[0x07] 735 1 T19 4 T40 41 T41 13
depth[0x08] 1596 1 T19 7 T40 44 T41 15
depth[0x09] 1913 1 T19 9 T40 80 T41 23
depth[0x0a] 53479 1 T19 247 T40 1952 T41 635



Summary for Variable msgfifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1548419 1 T1 360 T2 187 T16 40
auto[1] 100638155 1 T1 10373 T2 240 T3 20353



Summary for Variable msgfifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102133095 1 T1 10733 T2 427 T3 20353
auto[1] 53479 1 T19 247 T40 1952 T41 635

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%