Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100482491	1			T1	8192		T2	536		T3	19333
all_pins[1]	100482491	1			T1	8192		T2	536		T3	19333
all_pins[2]	100482491	1			T1	8192		T2	536		T3	19333

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300613902	1			T1	24498		T2	1531		T3	56666
values[0x1]	833571	1			T1	78		T2	77		T3	1333
transitions[0x0=>0x1]	831613	1			T1	78		T2	77		T3	1333
transitions[0x1=>0x0]	831637	1			T1	78		T2	77		T3	1333

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99972384	1			T1	8114		T2	459		T3	19161
all_pins[0]	values[0x1]	510107	1			T1	78		T2	77		T3	172
all_pins[0]	transitions[0x0=>0x1]	510090	1			T1	78		T2	77		T3	172
all_pins[0]	transitions[0x1=>0x0]	50	1			T176	2		T177	12		T178	2
all_pins[1]	values[0x0]	100482424	1			T1	8192		T2	536		T3	19333
all_pins[1]	values[0x1]	67	1			T176	2		T177	12		T178	2
all_pins[1]	transitions[0x0=>0x1]	56	1			T176	2		T177	12		T178	2
all_pins[1]	transitions[0x1=>0x0]	323386	1			T3	1161		T26	812		T30	776
all_pins[2]	values[0x0]	100159094	1			T1	8192		T2	536		T3	18172
all_pins[2]	values[0x1]	323397	1			T3	1161		T26	812		T30	776
all_pins[2]	transitions[0x0=>0x1]	321467	1			T3	1161		T26	812		T30	776
all_pins[2]	transitions[0x1=>0x0]	508201	1			T1	78		T2	77		T3	172