Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	700	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5699	1			T1	9		T3	15		T17	15
len_601_800	12786	1			T1	21		T3	34		T17	28
len_401_600	8529	1			T1	13		T3	20		T17	17
len_201_400	16616	1			T1	6		T3	13		T15	251
len_65_200	73779	1			T2	24		T3	5		T15	680
len_min_for_xof_require_squeeze	996	1			T15	10		T195	10		T87	9
len_keccak_block_sizes[72]	757	1			T15	5		T40	1		T65	1
len_keccak_block_sizes[104]	759	1			T15	5		T195	5		T23	1
len_keccak_block_sizes[136]	755	1			T2	1		T15	5		T37	1
len_keccak_block_sizes[144]	291	1			T15	5		T195	5		T196	5
len_keccak_block_sizes[168]	279	1			T15	5		T37	1		T195	5
len_datapath_width	14131	1			T2	4		T3	1		T14	246
len_2_63	214631	1			T1	32		T2	25		T3	7
len_1	53	1			T2	1		T37	1		T197	1