Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10885222 |
1 |
|
|
T1 |
9547 |
|
T2 |
2006 |
|
T3 |
18310 |
auto[1] |
25947919 |
1 |
|
|
T1 |
14692 |
|
T2 |
3750 |
|
T3 |
27866 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36713332 |
1 |
|
|
T1 |
24200 |
|
T2 |
5718 |
|
T3 |
46093 |
triple_byte_access |
39744 |
1 |
|
|
T1 |
16 |
|
T2 |
12 |
|
T3 |
22 |
halfword_access |
40247 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
28 |
byte_access |
39818 |
1 |
|
|
T1 |
13 |
|
T2 |
16 |
|
T3 |
33 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10765413 |
1 |
|
|
T1 |
9508 |
|
T2 |
1968 |
|
T3 |
18227 |
auto[0] |
triple_byte_access |
39744 |
1 |
|
|
T1 |
16 |
|
T2 |
12 |
|
T3 |
22 |
auto[0] |
halfword_access |
40247 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
28 |
auto[0] |
byte_access |
39818 |
1 |
|
|
T1 |
13 |
|
T2 |
16 |
|
T3 |
33 |
auto[1] |
word_access |
25947919 |
1 |
|
|
T1 |
14692 |
|
T2 |
3750 |
|
T3 |
27866 |