Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256278456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203910383

1

T1

100186

T2

1421

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	242747242	1			T1	127451		T2	1133		T3	1
values[0x0]	104410140	1			T1	551165		T2	527		T3	10
values[0x1]	113031457	1			T1	599455		T2	518		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199656005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

260532834

1

T1

131522

T2

1600

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1390837	1			T1	9455		T2	10		T4	3982
valid_sources[0x01]	2301083	1			T1	9383		T2	9		T4	4015
valid_sources[0x02]	1813043	1			T1	9396		T2	8		T4	2934
valid_sources[0x03]	1392517	1			T1	9512		T2	6		T4	3190
valid_sources[0x04]	1388590	1			T1	9417		T2	4		T4	3440
valid_sources[0x05]	1387865	1			T1	9529		T2	9		T4	3899
valid_sources[0x06]	1384538	1			T1	9538		T2	7		T4	3525
valid_sources[0x07]	1547212	1			T1	9547		T2	13		T4	4234
valid_sources[0x08]	1920024	1			T1	9379		T2	5		T4	4117
valid_sources[0x09]	1395111	1			T1	9408		T2	10		T4	3557
valid_sources[0x0a]	1392072	1			T1	9404		T2	7		T4	3726
valid_sources[0x0b]	1393161	1			T1	9494		T2	12		T4	3682
valid_sources[0x0c]	1389709	1			T1	9465		T2	8		T4	3725
valid_sources[0x0d]	1517749	1			T1	9304		T2	4		T4	3969
valid_sources[0x0e]	2257688	1			T1	9664		T2	8		T4	3548
valid_sources[0x0f]	1458544	1			T1	9502		T2	7		T4	3432
valid_sources[0x10]	1474880	1			T1	9493		T2	11		T4	3473
valid_sources[0x11]	3832109	1			T1	9580		T2	11		T4	3577
valid_sources[0x12]	2777110	1			T1	9494		T2	10		T4	3891
valid_sources[0x13]	1393926	1			T1	9560		T2	10		T4	3690
valid_sources[0x14]	1392239	1			T1	9436		T2	7		T4	3429
valid_sources[0x15]	1392913	1			T1	9605		T2	5		T4	3484
valid_sources[0x16]	1387295	1			T1	9606		T2	7		T4	3353
valid_sources[0x17]	1489185	1			T1	9484		T2	9		T4	4118
valid_sources[0x18]	1388734	1			T1	9386		T2	8		T4	3705
valid_sources[0x19]	1397705	1			T1	9454		T2	9		T4	3724
valid_sources[0x1a]	1382877	1			T1	9349		T2	9		T4	2998
valid_sources[0x1b]	1383429	1			T1	9565		T2	13		T4	3703
valid_sources[0x1c]	1856902	1			T1	9514		T2	6		T4	4065
valid_sources[0x1d]	1388269	1			T1	9464		T2	14		T4	3062
valid_sources[0x1e]	1397757	1			T1	9518		T2	10		T4	4192
valid_sources[0x1f]	1528424	1			T1	9423		T2	7		T4	3317
valid_sources[0x20]	1393325	1			T1	9213		T2	8		T4	3643
valid_sources[0x21]	1391761	1			T1	9370		T2	8		T4	4042
valid_sources[0x22]	1385842	1			T1	9408		T2	6		T4	3948
valid_sources[0x23]	1389547	1			T1	9379		T2	17		T4	3873
valid_sources[0x24]	1394135	1			T1	9517		T2	3		T4	3581
valid_sources[0x25]	1395940	1			T1	9534		T2	11		T4	3455
valid_sources[0x26]	1519982	1			T1	9433		T2	9		T4	3877
valid_sources[0x27]	1433512	1			T1	9451		T2	6		T4	4215
valid_sources[0x28]	3766409	1			T1	9570		T2	7		T4	3620
valid_sources[0x29]	1389325	1			T1	9455		T2	6		T4	3566
valid_sources[0x2a]	1394610	1			T1	9569		T2	9		T4	3414
valid_sources[0x2b]	1389458	1			T1	9607		T2	7		T3	22
valid_sources[0x2c]	1385354	1			T1	9398		T2	9		T4	4592
valid_sources[0x2d]	1396415	1			T1	9438		T2	11		T4	4256
valid_sources[0x2e]	2902724	1			T1	9475		T2	5		T4	4221
valid_sources[0x2f]	1425587	1			T1	9489		T2	4		T4	3976
valid_sources[0x30]	1387934	1			T1	9513		T2	6		T4	3984
valid_sources[0x31]	1845903	1			T1	9374		T2	12		T4	3449
valid_sources[0x32]	1435246	1			T1	9586		T2	6		T4	3801
valid_sources[0x33]	1384682	1			T1	9414		T2	9		T4	4018
valid_sources[0x34]	1391001	1			T1	9470		T2	11		T4	3963
valid_sources[0x35]	1394794	1			T1	9357		T2	6		T4	4474
valid_sources[0x36]	1394946	1			T1	9471		T2	7		T4	3850
valid_sources[0x37]	2530677	1			T1	9533		T2	10		T4	3222
valid_sources[0x38]	2435441	1			T1	9466		T2	6		T4	3529
valid_sources[0x39]	1475895	1			T1	9593		T2	10		T4	3673
valid_sources[0x3a]	1434522	1			T1	9418		T2	4		T4	4125
valid_sources[0x3b]	2067247	1			T1	9436		T2	12		T4	3873
valid_sources[0x3c]	2273218	1			T1	9447		T2	12		T4	3974
valid_sources[0x3d]	1843209	1			T1	9648		T2	15		T4	3743
valid_sources[0x3e]	1630073	1			T1	9467		T2	9		T4	2914
valid_sources[0x3f]	1388584	1			T1	9462		T2	9		T4	3417
valid_sources[0x40]	3424694	1			T1	9458		T2	13		T4	3893
valid_sources[0x41]	2014744	1			T1	9607		T2	3		T4	3720
valid_sources[0x42]	1390796	1			T1	9388		T2	6		T4	3929
valid_sources[0x43]	1503664	1			T1	9529		T2	9		T4	3067
valid_sources[0x44]	3935895	1			T1	9493		T2	4		T4	3618
valid_sources[0x45]	1391144	1			T1	9430		T2	12		T4	3522
valid_sources[0x46]	1565257	1			T1	9474		T2	5		T4	3487
valid_sources[0x47]	1417274	1			T1	9255		T2	11		T4	3880
valid_sources[0x48]	1424881	1			T1	9577		T2	12		T4	3781
valid_sources[0x49]	5135308	1			T1	9448		T2	11		T4	3956
valid_sources[0x4a]	1392492	1			T1	9493		T2	6		T4	3916
valid_sources[0x4b]	1414427	1			T1	9497		T2	7		T4	3996
valid_sources[0x4c]	1859189	1			T1	9526		T2	12		T4	3259
valid_sources[0x4d]	1490433	1			T1	9437		T2	9		T4	3671
valid_sources[0x4e]	3426127	1			T1	9380		T2	10		T4	3519
valid_sources[0x4f]	1849945	1			T1	9464		T2	10		T4	3850
valid_sources[0x50]	1382460	1			T1	9620		T2	8		T4	3914
valid_sources[0x51]	1398293	1			T1	9566		T2	6		T4	3586
valid_sources[0x52]	1388779	1			T1	9446		T2	9		T4	3618
valid_sources[0x53]	1510186	1			T1	9373		T2	8		T4	3854
valid_sources[0x54]	1391355	1			T1	9500		T2	5		T4	3873
valid_sources[0x55]	2311783	1			T1	9361		T2	9		T4	4019
valid_sources[0x56]	1844500	1			T1	9372		T2	10		T4	3432
valid_sources[0x57]	1390333	1			T1	9573		T2	11		T4	3901
valid_sources[0x58]	2326145	1			T1	9705		T2	4		T4	3284
valid_sources[0x59]	1407337	1			T1	9254		T2	5		T4	3286
valid_sources[0x5a]	1389615	1			T1	9454		T2	14		T4	3286
valid_sources[0x5b]	1389722	1			T1	9446		T2	8		T4	3439
valid_sources[0x5c]	1392111	1			T1	9444		T2	14		T4	3919
valid_sources[0x5d]	1645161	1			T1	9563		T2	11		T4	3863
valid_sources[0x5e]	1460301	1			T1	9408		T2	15		T4	3316
valid_sources[0x5f]	1384423	1			T1	9464		T2	9		T4	3237
valid_sources[0x60]	1394221	1			T1	9468		T2	3		T4	4118
valid_sources[0x61]	1389803	1			T1	9450		T2	4		T4	3198
valid_sources[0x62]	3474635	1			T1	9542		T2	7		T4	2952
valid_sources[0x63]	1390226	1			T1	9519		T2	3		T4	4084
valid_sources[0x64]	3999400	1			T1	9388		T2	9		T4	3384
valid_sources[0x65]	1427592	1			T1	9275		T2	13		T4	3356
valid_sources[0x66]	1387292	1			T1	9470		T2	9		T4	3570
valid_sources[0x67]	1386061	1			T1	9467		T2	4		T4	3930
valid_sources[0x68]	3816359	1			T1	9570		T2	5		T4	3212
valid_sources[0x69]	1396169	1			T1	9573		T2	14		T4	3147
valid_sources[0x6a]	5427350	1			T1	9462		T2	12		T4	3287
valid_sources[0x6b]	1443084	1			T1	9570		T2	9		T4	4462
valid_sources[0x6c]	1392030	1			T1	9213		T2	6		T4	3371
valid_sources[0x6d]	3808560	1			T1	9482		T2	8		T4	3562
valid_sources[0x6e]	1393673	1			T1	9470		T2	9		T4	3636
valid_sources[0x6f]	1533404	1			T1	9667		T2	6		T4	3823
valid_sources[0x70]	1403245	1			T1	9479		T2	16		T4	3973
valid_sources[0x71]	3854243	1			T1	9341		T2	12		T4	3990
valid_sources[0x72]	3796020	1			T1	9438		T2	9		T4	4242
valid_sources[0x73]	1386962	1			T1	9656		T2	6		T4	4042
valid_sources[0x74]	1395459	1			T1	9606		T2	10		T4	3164
valid_sources[0x75]	1432952	1			T1	9394		T2	6		T4	3295
valid_sources[0x76]	3970427	1			T1	9392		T2	5		T4	4097
valid_sources[0x77]	1418843	1			T1	9376		T2	4		T4	3229
valid_sources[0x78]	1389794	1			T1	9372		T2	6		T4	3865
valid_sources[0x79]	1386338	1			T1	9505		T2	6		T4	3931
valid_sources[0x7a]	1394132	1			T1	9512		T2	9		T4	3648
valid_sources[0x7b]	3177414	1			T1	9515		T2	9		T4	3489
valid_sources[0x7c]	2258525	1			T1	9491		T2	13		T4	3749
valid_sources[0x7d]	1605782	1			T1	9425		T2	13		T4	3728
valid_sources[0x7e]	3882101	1			T1	9524		T2	12		T4	3079
valid_sources[0x7f]	1403310	1			T1	9640		T2	12		T4	3721
valid_sources[0x80]	2311622	1			T1	9364		T2	13		T4	3068

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89068363

1

T1

427964

T2

704

T4

136677

values[0x0]

all_enables

biggest_size

61726934

1

T1

311223

T2

386

T3

4

values[0x1]

all_enables

biggest_size

53115086

1

T1

262681

T2

331

T3

4