Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260744231

1

T1

142326

T2

757

T3

14

full_word

204190155

1

T1

100186

T2

1421

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	464934076	1			T1	242513		T2	2178		T3	22
auto[TlIntgErrCmd]	97	1			T96	5		T97	5		T98	4
auto[TlIntgErrData]	89	1			T96	2		T97	5		T151	2
auto[TlIntgErrBoth]	124	1			T96	3		T97	10		T98	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243614842

1

T1

127451

T2

1133

T3

1

auto[1]

221319544

1

T1

115062

T2

1045

T3

21

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154476063	1			T1	846552		T2	429		T3	1
auto[TlIntgErrNone]	partial	auto[1]	106267876	1			T1	576716		T2	328		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	89138648	1			T1	427964		T2	704		T4	136677
auto[TlIntgErrNone]	full_word	auto[1]	115051489	1			T1	573904		T2	717		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T96	1		T97	4		T98	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T96	4		T97	1		T98	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T148	1		T133	1		T149	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T152	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	34	1			T96	1		T148	2		T153	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T96	1		T97	5		T151	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T151	1		T133	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T133	1		T155	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T96	2		T97	1		T98	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T96	1		T97	8		T98	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T147	1		T154	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T97	1		T155	1		-	-