Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1045895	0	0
entropy_period_rd_A	2147483647	2059	0	0
intr_enable_rd_A	2147483647	2984	0	0
prefix_0_rd_A	2147483647	2339	0	0
prefix_10_rd_A	2147483647	2381	0	0
prefix_1_rd_A	2147483647	2186	0	0
prefix_2_rd_A	2147483647	2449	0	0
prefix_3_rd_A	2147483647	2385	0	0
prefix_4_rd_A	2147483647	2424	0	0
prefix_5_rd_A	2147483647	2265	0	0
prefix_6_rd_A	2147483647	2249	0	0
prefix_7_rd_A	2147483647	2476	0	0
prefix_8_rd_A	2147483647	2251	0	0
prefix_9_rd_A	2147483647	2370	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1045895	0	0
T31	184748	25666	0	0
T32	121545	150714	0	0
T33	0	39179	0	0
T45	0	14760	0	0
T46	0	82497	0	0
T73	0	53911	0	0
T103	0	30829	0	0
T104	0	125443	0	0
T105	0	131147	0	0
T106	0	30288	0	0
T107	173207	0	0	0
T108	6220	0	0	0
T109	863690	0	0	0
T110	37759	0	0	0
T111	469140	0	0	0
T112	426463	0	0	0
T113	180454	0	0	0
T114	203825	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2059	0	0
T84	11265	66	0	0
T97	22667	133	0	0
T124	4900	13	0	0
T125	6100	30	0	0
T126	7836	18	0	0
T127	144560	202	0	0
T128	144084	181	0	0
T129	1797	7	0	0
T130	52451	426	0	0
T131	2466	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2984	0	0
T84	11265	124	0	0
T97	22667	168	0	0
T125	6100	12	0	0
T126	7836	22	0	0
T127	144560	460	0	0
T128	144084	446	0	0
T129	1797	3	0	0
T130	52451	425	0	0
T131	2466	13	0	0
T132	2988	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2339	0	0
T84	11265	48	0	0
T97	22667	82	0	0
T124	4900	21	0	0
T125	6100	28	0	0
T126	7836	24	0	0
T127	144560	416	0	0
T128	144084	440	0	0
T129	1797	3	0	0
T130	52451	425	0	0
T132	2988	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T84	11265	59	0	0
T97	22667	78	0	0
T126	7836	18	0	0
T127	144560	433	0	0
T128	144084	495	0	0
T129	1797	7	0	0
T130	52451	449	0	0
T131	2466	1	0	0
T132	2988	11	0	0
T133	24790	97	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2186	0	0
T84	11265	36	0	0
T97	22667	72	0	0
T125	6100	12	0	0
T126	7836	10	0	0
T127	144560	430	0	0
T128	144084	441	0	0
T129	1797	7	0	0
T130	52451	407	0	0
T131	2466	5	0	0
T132	2988	9	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2449	0	0
T84	11265	74	0	0
T97	22667	74	0	0
T124	4900	13	0	0
T125	6100	63	0	0
T126	7836	10	0	0
T127	144560	449	0	0
T128	144084	462	0	0
T129	1797	7	0	0
T130	52451	410	0	0
T132	2988	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T84	11265	30	0	0
T97	22667	98	0	0
T124	4900	6	0	0
T125	6100	13	0	0
T126	7836	24	0	0
T127	144560	411	0	0
T128	144084	490	0	0
T129	1797	5	0	0
T130	52451	420	0	0
T132	2988	15	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2424	0	0
T84	11265	39	0	0
T97	22667	87	0	0
T124	4900	5	0	0
T125	6100	26	0	0
T126	7836	21	0	0
T127	144560	484	0	0
T128	144084	483	0	0
T129	1797	9	0	0
T130	52451	405	0	0
T132	2988	7	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2265	0	0
T84	11265	56	0	0
T97	22667	62	0	0
T124	4900	32	0	0
T125	6100	20	0	0
T126	7836	2	0	0
T127	144560	438	0	0
T128	144084	472	0	0
T129	1797	4	0	0
T130	52451	411	0	0
T132	2988	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2249	0	0
T84	11265	54	0	0
T97	22667	67	0	0
T124	4900	9	0	0
T125	6100	16	0	0
T126	7836	14	0	0
T127	144560	437	0	0
T128	144084	475	0	0
T129	1797	4	0	0
T130	52451	380	0	0
T132	2988	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2476	0	0
T84	11265	48	0	0
T97	22667	97	0	0
T124	4900	9	0	0
T125	6100	12	0	0
T126	7836	4	0	0
T127	144560	497	0	0
T128	144084	474	0	0
T129	1797	1	0	0
T130	52451	434	0	0
T132	2988	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T84	11265	58	0	0
T97	22667	70	0	0
T125	6100	1	0	0
T126	7836	12	0	0
T127	144560	465	0	0
T128	144084	460	0	0
T129	1797	6	0	0
T130	52451	446	0	0
T131	2466	9	0	0
T132	2988	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2370	0	0
T84	11265	72	0	0
T97	22667	72	0	0
T124	4900	1	0	0
T125	6100	23	0	0
T126	7836	15	0	0
T127	144560	421	0	0
T128	144084	495	0	0
T129	1797	4	0	0
T130	52451	447	0	0
T132	2988	17	0	0