Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

250992513

1

T1

6144

T2

46472

T3

263015

full_word

197755788

1

T1

9918

T2

77360

T3

183843

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448748011	1			T1	16062		T2	123832		T3	446858
auto[TlIntgErrCmd]	92	1			T54	5		T130	3		T131	1
auto[TlIntgErrData]	107	1			T54	2		T130	3		T131	4
auto[TlIntgErrBoth]	91	1			T54	3		T130	4		T131	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237061909

1

T1

11174

T2

83223

T3

230481

auto[1]

211686392

1

T1

4888

T2

40609

T3

216377

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	150529698	1			T1	3928		T2	28397		T3	160701
auto[TlIntgErrNone]	partial	auto[1]	100462545	1			T1	2216		T2	18075		T3	102314
auto[TlIntgErrNone]	full_word	auto[0]	86532070	1			T1	7246		T2	54826		T3	69780
auto[TlIntgErrNone]	full_word	auto[1]	111223698	1			T1	2672		T2	22534		T3	114063
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T54	3		T130	2		T131	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T54	2		T130	1		T187	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T195	1		T192	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T190	1		T196	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1			T54	1		T131	3		T187	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T130	2		T187	9		T190	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T54	1		T131	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T130	1		T191	1		T197	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T130	1		T131	3		T187	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T54	2		T130	2		T131	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T131	1		T192	1		T194	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T54	1		T130	1		T195	1