Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	98.80	100.00	100.00		100.00	94.00	100.00

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.80	100.00	100.00		100.00	94.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	100.00	100.00	100.00	94.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		69	69	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	6	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T116
1	0	Covered	T1,T2,T13

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T116

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T13

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T1,T2,T13
StKmacFlush	208	Covered	T1,T2,T13
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T1,T2,T13
StTerminalError	241	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T1,T2,T13
StKey->StTerminalError	241	Covered	T5,T59,T60
StKmacFlush->StKmacIdle	218	Covered	T1,T2,T13
StKmacFlush->StTerminalError	241	Covered	T57
StKmacIdle->StKey	181	Covered	T1,T2,T13
StKmacIdle->StTerminalError	241	Covered	T4,T8,T9
StKmacMsg->StKmacFlush	208	Covered	T1,T2,T13
StKmacMsg->StTerminalError	241	Covered	T6,T7,T117

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		50	47	94.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	4	100.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T1,T2,T13
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T1,T2,T13
StKey	-	0	-	-	Covered	T1,T2,T13
StKmacMsg	-	-	1	-	Covered	T1,T2,T13
StKmacMsg	-	-	0	-	Covered	T1,T2,T13
StKmacFlush	-	-	-	1	Covered	T1,T2,T13
StKmacFlush	-	-	-	0	Covered	T1,T2,T13
StTerminalError	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T116
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T13
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T3,T13
Key512	Covered	T3,T13,T14
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T13,T14,T70
L256	Covered	T1,T2,T3
L384	Covered	T13,T17,T18
L512	Covered	T3,T68,T70
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T3,T13
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T3,T13
Key512	Covered	T3,T13,T14
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	7318756	0	0
KeyDataStableWhenValid_M	2147483647	344432329	0	0
KeyLengthStableWhenValid_M	2147483647	344432329	0	0
KmacEnStable_M	2147483647	21973	0	0
MaxKeyLenMatchToKey512_A	1022	1022	0	0
ModeStable_M	2147483647	33576	0	0
ProcessLatchedCleared_A	2147483647	1	0	0
StrengthStable_M	2147483647	40072	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7318756	0	0
T1	36434	457	0	0
T2	862867	5742	0	0
T3	471574	0	0	0
T13	144731	6086	0	0
T14	821711	12896	0	0
T15	6237	109	0	0
T16	214851	19491	0	0
T17	135338	0	0	0
T18	717503	0	0	0
T19	371687	5164	0	0
T26	0	5360	0	0
T27	0	2623	0	0
T70	0	245	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	344432329	0	0
T1	36434	14962	0	0
T2	862867	596774	0	0
T3	471574	0	0	0
T13	144731	691861	0	0
T14	821711	591261	0	0
T15	6237	4502	0	0
T16	214851	162568	0	0
T17	135338	0	0	0
T18	717503	0	0	0
T19	371687	202274	0	0
T26	0	640256	0	0
T27	0	165350	0	0
T70	0	80803	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	344432329	0	0
T1	36434	14962	0	0
T2	862867	596774	0	0
T3	471574	0	0	0
T13	144731	691861	0	0
T14	821711	591261	0	0
T15	6237	4502	0	0
T16	214851	162568	0	0
T17	135338	0	0	0
T18	717503	0	0	0
T19	371687	202274	0	0
T26	0	640256	0	0
T27	0	165350	0	0
T70	0	80803	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21973	0	0
T1	36434	12	0	0
T2	862867	45	0	0
T3	471574	0	0	0
T13	144731	109	0	0
T14	821711	27	0	0
T15	6237	1	0	0
T16	214851	13	0	0
T17	135338	0	0	0
T18	717503	0	0	0
T19	371687	71	0	0
T20	0	30	0	0
T26	0	79	0	0
T27	0	44	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33576	0	0
T1	36434	13	0	0
T2	862867	45	0	0
T3	471574	0	0	0
T13	144731	185	0	0
T14	821711	29	0	0
T15	6237	1	0	0
T16	214851	13	0	0
T17	135338	0	0	0
T18	717503	0	0	0
T19	371687	139	0	0
T20	0	33	0	0
T35	0	1	0	0
T36	0	1	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1	0	0
T116	82425	1	0	0
T118	615800	0	0	0
T119	190777	0	0	0
T120	68280	0	0	0
T121	332834	0	0	0
T122	393400	0	0	0
T123	2775	0	0	0
T124	262003	0	0	0
T125	293616	0	0	0
T126	259978	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40072	0	0
T1	36434	12	0	0
T2	862867	57	0	0
T3	471574	2	0	0
T13	144731	181	0	0
T14	821711	38	0	0
T15	6237	2	0	0
T16	214851	16	0	0
T17	135338	2	0	0
T18	717503	2	0	0
T19	371687	138	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	36434	36348	0	0
T2	862867	862810	0	0
T3	471574	471567	0	0
T13	144731	144723	0	0
T14	821711	821425	0	0
T15	6237	6160	0	0
T16	214851	214845	0	0
T17	135338	135331	0	0
T18	717503	717493	0	0
T19	371687	371616	0	0