Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	63540	0	0
entropy_period_rd_A	2147483647	1817	0	0
intr_enable_rd_A	2147483647	2641	0	0
prefix_0_rd_A	2147483647	1607	0	0
prefix_10_rd_A	2147483647	1786	0	0
prefix_1_rd_A	2147483647	1811	0	0
prefix_2_rd_A	2147483647	1661	0	0
prefix_3_rd_A	2147483647	1828	0	0
prefix_4_rd_A	2147483647	1740	0	0
prefix_5_rd_A	2147483647	1797	0	0
prefix_6_rd_A	2147483647	1687	0	0
prefix_7_rd_A	2147483647	1789	0	0
prefix_8_rd_A	2147483647	1779	0	0
prefix_9_rd_A	2147483647	1795	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	63540	0	0
T52	914646	60846	0	0
T53	0	1	0	0
T54	0	1	0	0
T127	0	35	0	0
T128	0	183	0	0
T129	0	113	0	0
T132	0	40	0	0
T136	0	122	0	0
T139	0	3	0	0
T140	0	2	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1817	0	0
T52	914646	49	0	0
T53	0	6	0	0
T95	0	37	0	0
T96	0	5	0	0
T98	0	15	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	21	0	0
T161	0	21	0	0
T162	0	202	0	0
T163	0	16	0	0
T164	0	57	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T52	914646	72	0	0
T53	0	12	0	0
T95	0	53	0	0
T98	0	16	0	0
T133	0	22	0	0
T135	0	32	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	2	0	0
T161	0	30	0	0
T162	0	190	0	0
T165	0	23	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T52	914646	65	0	0
T53	0	10	0	0
T95	0	25	0	0
T98	0	10	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	16	0	0
T161	0	4	0	0
T162	0	222	0	0
T164	0	26	0	0
T166	0	4	0	0
T167	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1786	0	0
T52	914646	87	0	0
T53	0	2	0	0
T95	0	26	0	0
T98	0	23	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	35	0	0
T161	0	11	0	0
T162	0	249	0	0
T163	0	23	0	0
T168	0	1	0	0
T169	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1811	0	0
T52	914646	107	0	0
T53	0	9	0	0
T95	0	28	0	0
T98	0	14	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	19	0	0
T161	0	9	0	0
T162	0	234	0	0
T163	0	14	0	0
T164	0	31	0	0
T168	0	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1661	0	0
T52	914646	84	0	0
T53	0	3	0	0
T95	0	23	0	0
T98	0	1	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	6	0	0
T161	0	10	0	0
T162	0	241	0	0
T163	0	33	0	0
T164	0	34	0	0
T168	0	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1828	0	0
T52	914646	57	0	0
T53	0	6	0	0
T95	0	20	0	0
T98	0	10	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	5	0	0
T161	0	1	0	0
T162	0	240	0	0
T163	0	5	0	0
T168	0	4	0	0
T169	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1740	0	0
T52	914646	63	0	0
T53	0	12	0	0
T95	0	35	0	0
T96	0	7	0	0
T98	0	9	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	20	0	0
T161	0	12	0	0
T162	0	196	0	0
T163	0	37	0	0
T169	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T52	914646	95	0	0
T53	0	10	0	0
T95	0	26	0	0
T96	0	8	0	0
T98	0	19	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	61	0	0
T161	0	11	0	0
T162	0	235	0	0
T163	0	23	0	0
T168	0	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1687	0	0
T52	914646	80	0	0
T53	0	13	0	0
T95	0	17	0	0
T98	0	10	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	11	0	0
T161	0	7	0	0
T162	0	224	0	0
T163	0	47	0	0
T164	0	26	0	0
T169	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T52	914646	125	0	0
T53	0	3	0	0
T95	0	34	0	0
T98	0	12	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	35	0	0
T161	0	18	0	0
T162	0	225	0	0
T163	0	36	0	0
T164	0	22	0	0
T166	0	20	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1779	0	0
T52	914646	83	0	0
T53	0	7	0	0
T95	0	34	0	0
T98	0	13	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	23	0	0
T161	0	5	0	0
T162	0	234	0	0
T163	0	47	0	0
T164	0	39	0	0
T168	0	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T52	914646	99	0	0
T53	0	11	0	0
T95	0	28	0	0
T98	0	14	0	0
T142	531134	0	0	0
T143	428205	0	0	0
T144	439794	0	0	0
T145	6164	0	0	0
T146	649108	0	0	0
T147	65184	0	0	0
T148	476540	0	0	0
T149	812300	0	0	0
T150	181158	0	0	0
T160	0	31	0	0
T161	0	7	0	0
T162	0	190	0	0
T163	0	12	0	0
T168	0	2	0	0
T169	0	4	0	0