Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253666172

1

T1

629

T2

501

T3

7116

full_word

197079941

1

T1

1411

T2

14168

T3

12748

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450745813	1			T1	2040		T2	14669		T3	19864
auto[TlIntgErrCmd]	117	1			T46	3		T123	9		T124	4
auto[TlIntgErrData]	87	1			T46	3		T123	8		T124	5
auto[TlIntgErrBoth]	96	1			T46	4		T123	3		T124	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238060201

1

T1

1065

T2

12355

T3

13530

auto[1]

212685912

1

T1

975

T2

2314

T3

6334

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151907793	1			T1	385		T2	247		T3	4332
auto[TlIntgErrNone]	partial	auto[1]	101758099	1			T1	244		T2	254		T3	2784
auto[TlIntgErrNone]	full_word	auto[0]	86152274	1			T1	680		T2	12108		T3	9198
auto[TlIntgErrNone]	full_word	auto[1]	110927647	1			T1	731		T2	2060		T3	3550
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T46	3		T123	5		T124	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T123	4		T124	2		T178	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T182	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T183	1		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T46	1		T123	4		T124	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T46	2		T123	3		T124	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T124	1		T183	1		T186	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T123	1		T178	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T46	1		T123	2		T178	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T46	3		T123	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T178	1		T185	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T187	1		T188	1		T189	1