Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	77590	0	0
entropy_period_rd_A	2147483647	1621	0	0
intr_enable_rd_A	2147483647	2476	0	0
prefix_0_rd_A	2147483647	1561	0	0
prefix_10_rd_A	2147483647	1572	0	0
prefix_1_rd_A	2147483647	1678	0	0
prefix_2_rd_A	2147483647	1646	0	0
prefix_3_rd_A	2147483647	1446	0	0
prefix_4_rd_A	2147483647	1509	0	0
prefix_5_rd_A	2147483647	1527	0	0
prefix_6_rd_A	2147483647	1600	0	0
prefix_7_rd_A	2147483647	1458	0	0
prefix_8_rd_A	2147483647	1655	0	0
prefix_9_rd_A	2147483647	1656	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	77590	0	0
T25	388534	34982	0	0
T45	0	39234	0	0
T114	794861	0	0	0
T122	0	3	0	0
T123	0	3	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	4	0	0
T128	0	105	0	0
T129	0	18	0	0
T133	0	135	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1621	0	0
T25	388534	47	0	0
T96	0	80	0	0
T105	0	1	0	0
T114	794861	0	0	0
T123	0	122	0	0
T124	0	76	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	47	0	0
T156	0	4	0	0
T157	0	54	0	0
T158	0	177	0	0
T159	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2476	0	0
T25	388534	100	0	0
T96	0	95	0	0
T114	794861	0	0	0
T123	0	185	0	0
T124	0	49	0	0
T132	0	6	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	88	0	0
T156	0	7	0	0
T157	0	56	0	0
T160	0	1	0	0
T161	0	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T25	388534	83	0	0
T96	0	39	0	0
T114	794861	0	0	0
T123	0	90	0	0
T124	0	37	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	66	0	0
T156	0	3	0	0
T157	0	17	0	0
T158	0	210	0	0
T159	0	13	0	0
T162	0	31	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572	0	0
T25	388534	107	0	0
T96	0	60	0	0
T105	0	1	0	0
T114	794861	0	0	0
T123	0	81	0	0
T124	0	34	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	57	0	0
T157	0	28	0	0
T158	0	189	0	0
T159	0	3	0	0
T162	0	26	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T25	388534	131	0	0
T96	0	68	0	0
T105	0	3	0	0
T114	794861	0	0	0
T123	0	96	0	0
T124	0	43	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	27	0	0
T156	0	5	0	0
T157	0	26	0	0
T158	0	201	0	0
T160	0	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1646	0	0
T25	388534	117	0	0
T96	0	68	0	0
T105	0	6	0	0
T114	794861	0	0	0
T123	0	95	0	0
T124	0	35	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	49	0	0
T156	0	4	0	0
T157	0	9	0	0
T158	0	210	0	0
T160	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1446	0	0
T25	388534	72	0	0
T96	0	56	0	0
T114	794861	0	0	0
T123	0	85	0	0
T124	0	35	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	5	0	0
T156	0	2	0	0
T157	0	27	0	0
T158	0	182	0	0
T159	0	4	0	0
T160	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1509	0	0
T25	388534	80	0	0
T96	0	60	0	0
T105	0	5	0	0
T114	794861	0	0	0
T123	0	75	0	0
T124	0	40	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	37	0	0
T156	0	1	0	0
T157	0	25	0	0
T158	0	202	0	0
T159	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1527	0	0
T25	388534	73	0	0
T96	0	48	0	0
T105	0	1	0	0
T114	794861	0	0	0
T123	0	85	0	0
T124	0	45	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	36	0	0
T156	0	1	0	0
T157	0	29	0	0
T158	0	194	0	0
T160	0	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1600	0	0
T25	388534	80	0	0
T96	0	57	0	0
T114	794861	0	0	0
T123	0	85	0	0
T124	0	38	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	40	0	0
T156	0	1	0	0
T157	0	24	0	0
T158	0	264	0	0
T159	0	9	0	0
T160	0	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T25	388534	86	0	0
T96	0	59	0	0
T105	0	2	0	0
T114	794861	0	0	0
T123	0	94	0	0
T124	0	25	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	46	0	0
T156	0	4	0	0
T157	0	19	0	0
T158	0	222	0	0
T159	0	12	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1655	0	0
T25	388534	69	0	0
T96	0	39	0	0
T105	0	8	0	0
T114	794861	0	0	0
T123	0	84	0	0
T124	0	38	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	43	0	0
T156	0	4	0	0
T157	0	18	0	0
T158	0	253	0	0
T160	0	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T25	388534	108	0	0
T96	0	55	0	0
T105	0	3	0	0
T114	794861	0	0	0
T123	0	85	0	0
T124	0	45	0	0
T137	700359	0	0	0
T138	487221	0	0	0
T139	24507	0	0	0
T140	960848	0	0	0
T141	255195	0	0	0
T142	89604	0	0	0
T143	208274	0	0	0
T144	70446	0	0	0
T155	0	18	0	0
T156	0	3	0	0
T157	0	27	0	0
T158	0	219	0	0
T160	0	7	0	0