SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
93.33 | 93.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_errors_cgs_wrap[kmac_reg_block] | 93.33 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
93.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 1 | 14 | 93.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 2 | |
cp_mem_ro_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_wo_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 62227 | 1 | T35 | 58255 | T50 | 3 | T51 | 3 | ||||
auto[1] | 11679 | 1 | T35 | 10926 | T115 | 47 | T118 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 62855 | 1 | T35 | 58763 | T50 | 3 | T51 | 3 | ||||
auto[1] | 11051 | 1 | T35 | 10418 | T115 | 29 | T118 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 73906 | 1 | T35 | 69181 | T50 | 3 | T51 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 73871 | 1 | T35 | 69152 | T50 | 3 | T51 | 3 | ||||
auto[1] | 35 | 1 | T35 | 29 | T121 | 1 | T175 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 69958 | 1 | T35 | 65565 | T50 | 3 | T51 | 3 | ||||
auto[1] | 3948 | 1 | T35 | 3616 | T115 | 16 | T116 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 28006 | 1 | T35 | 26228 | T115 | 140 | T116 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 71918 | 1 | T35 | 67295 | T50 | 3 | T51 | 3 | ||||
auto[1] | 1988 | 1 | T35 | 1886 | T115 | 14 | T119 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 56802 | 1 | T35 | 53103 | T50 | 3 | T51 | 3 | ||||
auto[1] | 17104 | 1 | T35 | 16078 | T115 | 39 | T116 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |