Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254219791

1

T1

5274

T2

213825

T3

44669

full_word

198072420

1

T1

27412

T2

176736

T3

84020

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452291901	1			T1	32686		T2	390561		T3	128689
auto[TlIntgErrCmd]	89	1			T50	2		T51	5		T117	1
auto[TlIntgErrData]	100	1			T50	2		T51	1		T117	5
auto[TlIntgErrBoth]	121	1			T50	6		T51	4		T117	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238949718

1

T1

11115

T2

206646

T3

89113

auto[1]

213342493

1

T1

21571

T2

183915

T3

39576

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152402670	1			T1	4928		T2	130424		T3	26801
auto[TlIntgErrNone]	partial	auto[1]	101816841	1			T1	346		T2	83401		T3	17868
auto[TlIntgErrNone]	full_word	auto[0]	86546911	1			T1	6187		T2	76222		T3	62312
auto[TlIntgErrNone]	full_word	auto[1]	111525479	1			T1	21225		T2	100514		T3	21708
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T50	1		T51	2		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T50	1		T51	3		T132	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T132	1		T179	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T179	1		T181	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T117	3		T132	2		T143	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T50	2		T51	1		T132	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T117	1		T132	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T117	1		T179	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T50	3		T51	1		T132	5
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T50	3		T51	3		T117	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T143	1		T134	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T132	1		T125	2		T183	1