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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 309004894 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1230 1230 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 309004894 0 0
T1 69304 6115 0 0
T2 268499 266822 0 0
T3 193490 58753 0 0
T4 3382 104 0 0
T13 480677 330272 0 0
T14 12771 640 0 0
T15 943418 332688 0 0
T16 173572 173614 0 0
T17 471754 34698 0 0
T18 145099 139774 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1230 1230 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 637863421 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1230 1230 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 637863421 0 0
T1 69304 6115 0 0
T2 268499 266822 0 0
T3 193490 266869 0 0
T4 3382 104 0 0
T13 480677 148653 0 0
T14 12771 640 0 0
T15 943418 332688 0 0
T16 173572 173614 0 0
T17 471754 34698 0 0
T18 145099 139774 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 69304 69205 0 0
T2 268499 268482 0 0
T3 193490 193485 0 0
T4 3382 3270 0 0
T13 480677 480671 0 0
T14 12771 12715 0 0
T15 943418 943337 0 0
T16 173572 173571 0 0
T17 471754 471664 0 0
T18 145099 145099 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1230 1230 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

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