Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	53292	0	0
entropy_period_rd_A	2147483647	1223	0	0
intr_enable_rd_A	2147483647	2167	0	0
prefix_0_rd_A	2147483647	1432	0	0
prefix_10_rd_A	2147483647	1330	0	0
prefix_1_rd_A	2147483647	1304	0	0
prefix_2_rd_A	2147483647	1378	0	0
prefix_3_rd_A	2147483647	1311	0	0
prefix_4_rd_A	2147483647	1394	0	0
prefix_5_rd_A	2147483647	1431	0	0
prefix_6_rd_A	2147483647	1245	0	0
prefix_7_rd_A	2147483647	1403	0	0
prefix_8_rd_A	2147483647	1404	0	0
prefix_9_rd_A	2147483647	1335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53292	0	0
T12	271352	0	0	0
T35	460132	50253	0	0
T51	0	2	0	0
T115	0	246	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	3	0	0
T119	0	112	0	0
T130	0	6	0	0
T132	0	3	0	0
T133	0	3	0	0
T135	40241	0	0	0
T136	643483	0	0	0
T137	953838	0	0	0
T138	395920	0	0	0
T139	24708	0	0	0
T140	26393	0	0	0
T141	904938	0	0	0
T142	237403	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223	0	0
T106	11971	83	0	0
T116	10048	16	0	0
T117	11441	52	0	0
T130	7267	4	0	0
T133	8141	11	0	0
T143	11088	18	0	0
T155	6374	22	0	0
T156	10301	26	0	0
T157	8296	14	0	0
T158	7235	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2167	0	0
T116	10048	38	0	0
T117	11441	88	0	0
T130	7267	4	0	0
T133	8141	7	0	0
T143	11088	69	0	0
T155	6374	15	0	0
T156	10301	29	0	0
T159	1388	24	0	0
T160	1089	21	0	0
T161	1066	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1432	0	0
T106	11971	44	0	0
T111	2522	1	0	0
T116	10048	26	0	0
T117	11441	47	0	0
T130	7267	13	0	0
T133	8141	8	0	0
T143	11088	22	0	0
T155	6374	26	0	0
T156	10301	67	0	0
T158	7235	9	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1330	0	0
T106	11971	49	0	0
T111	2522	6	0	0
T116	10048	22	0	0
T117	11441	44	0	0
T130	7267	12	0	0
T133	8141	12	0	0
T143	11088	8	0	0
T155	6374	23	0	0
T156	10301	48	0	0
T157	8296	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304	0	0
T106	11971	51	0	0
T111	2522	6	0	0
T116	10048	14	0	0
T117	11441	38	0	0
T130	7267	1	0	0
T133	8141	16	0	0
T143	11088	17	0	0
T155	6374	6	0	0
T156	10301	7	0	0
T157	8296	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378	0	0
T106	11971	51	0	0
T111	2522	6	0	0
T116	10048	6	0	0
T117	11441	42	0	0
T130	7267	10	0	0
T133	8141	19	0	0
T143	11088	36	0	0
T155	6374	15	0	0
T156	10301	37	0	0
T157	8296	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T106	11971	51	0	0
T111	2522	1	0	0
T116	10048	13	0	0
T117	11441	39	0	0
T130	7267	4	0	0
T133	8141	6	0	0
T143	11088	40	0	0
T155	6374	21	0	0
T156	10301	36	0	0
T157	8296	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1394	0	0
T106	11971	55	0	0
T111	2522	9	0	0
T116	10048	21	0	0
T117	11441	29	0	0
T130	7267	6	0	0
T133	8141	4	0	0
T143	11088	27	0	0
T155	6374	33	0	0
T156	10301	21	0	0
T157	8296	26	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1431	0	0
T106	11971	50	0	0
T111	2522	2	0	0
T116	10048	12	0	0
T117	11441	25	0	0
T130	7267	16	0	0
T133	8141	9	0	0
T143	11088	14	0	0
T155	6374	4	0	0
T156	10301	37	0	0
T157	8296	19	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1245	0	0
T106	11971	42	0	0
T111	2522	2	0	0
T116	10048	20	0	0
T117	11441	36	0	0
T130	7267	3	0	0
T133	8141	6	0	0
T143	11088	16	0	0
T155	6374	4	0	0
T156	10301	32	0	0
T158	7235	20	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1403	0	0
T106	11971	65	0	0
T111	2522	6	0	0
T116	10048	25	0	0
T117	11441	54	0	0
T130	7267	11	0	0
T133	8141	12	0	0
T143	11088	19	0	0
T155	6374	29	0	0
T156	10301	17	0	0
T157	8296	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1404	0	0
T106	11971	65	0	0
T111	2522	7	0	0
T116	10048	20	0	0
T117	11441	43	0	0
T130	7267	20	0	0
T133	8141	9	0	0
T143	11088	2	0	0
T155	6374	12	0	0
T156	10301	48	0	0
T157	8296	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T106	11971	64	0	0
T111	2522	3	0	0
T116	10048	16	0	0
T117	11441	36	0	0
T133	8141	10	0	0
T143	11088	10	0	0
T155	6374	5	0	0
T156	10301	38	0	0
T157	8296	17	0	0
T158	7235	22	0	0