Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253687709	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198831040

1

T1

887497

T2

261811

T3

888291

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239262696	1			T1	112139		T2	338299		T3	109650
values[0x0]	102523844	1			T1	452593		T2	154867		T3	445425
values[0x1]	110732209	1			T1	491383		T2	166870		T3	479131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197830996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254687753

1

T1

114844

T2

348850

T3

113503

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1991579	1			T1	8055		T2	2509		T13	1871
valid_sources[0x01]	1325618	1			T1	7874		T2	2647		T13	2000
valid_sources[0x02]	1339152	1			T1	8203		T2	2589		T13	1818
valid_sources[0x03]	1796746	1			T1	8173		T2	2579		T13	1796
valid_sources[0x04]	3544528	1			T1	8165		T2	2682		T13	1895
valid_sources[0x05]	3393883	1			T1	8175		T2	2466		T13	1865
valid_sources[0x06]	1383673	1			T1	8005		T2	2469		T13	1818
valid_sources[0x07]	1333986	1			T1	7986		T2	2544		T13	1916
valid_sources[0x08]	1327809	1			T1	7962		T2	2672		T13	1734
valid_sources[0x09]	1329363	1			T1	8019		T2	2529		T13	1858
valid_sources[0x0a]	1327501	1			T1	8003		T2	2602		T13	1710
valid_sources[0x0b]	1332462	1			T1	8182		T2	2431		T13	1665
valid_sources[0x0c]	2160461	1			T1	8111		T2	2496		T13	1807
valid_sources[0x0d]	3329628	1			T1	7988		T2	2523		T13	1753
valid_sources[0x0e]	1483865	1			T1	8106		T2	2415		T13	1864
valid_sources[0x0f]	1660510	1			T1	8067		T2	2560		T13	2021
valid_sources[0x10]	1337171	1			T1	8108		T2	2683		T13	1695
valid_sources[0x11]	2318656	1			T1	7798		T2	2421		T13	1905
valid_sources[0x12]	1358948	1			T1	8138		T2	2592		T13	1835
valid_sources[0x13]	1334018	1			T1	7958		T2	2607		T13	1816
valid_sources[0x14]	2484282	1			T1	8132		T2	2437		T13	1865
valid_sources[0x15]	1338038	1			T1	7834		T2	2500		T13	1868
valid_sources[0x16]	1341484	1			T1	8075		T2	2591		T13	1916
valid_sources[0x17]	2286192	1			T1	8155		T2	2580		T13	1880
valid_sources[0x18]	1432587	1			T1	8127		T2	2507		T13	1938
valid_sources[0x19]	1334924	1			T1	7830		T2	2642		T13	1841
valid_sources[0x1a]	1671387	1			T1	8103		T2	2523		T13	1794
valid_sources[0x1b]	2197605	1			T1	8189		T2	2615		T13	1790
valid_sources[0x1c]	1334671	1			T1	8006		T2	2522		T13	1887
valid_sources[0x1d]	1336099	1			T1	8157		T2	2431		T13	1887
valid_sources[0x1e]	1333668	1			T1	8020		T2	2761		T13	1951
valid_sources[0x1f]	1329665	1			T1	8293		T2	2523		T13	1938
valid_sources[0x20]	5885959	1			T1	8101		T2	2532		T13	1851
valid_sources[0x21]	1336980	1			T1	8108		T2	2584		T13	1983
valid_sources[0x22]	1348658	1			T1	8070		T2	2894		T13	1693
valid_sources[0x23]	1341057	1			T1	8210		T2	2556		T13	1944
valid_sources[0x24]	3763673	1			T1	7823		T2	2625		T13	1861
valid_sources[0x25]	1336671	1			T1	8001		T2	2518		T13	1846
valid_sources[0x26]	1494164	1			T1	8050		T2	2713		T13	1867
valid_sources[0x27]	1334746	1			T1	8007		T2	2538		T13	1778
valid_sources[0x28]	1384709	1			T1	8123		T2	2617		T13	1703
valid_sources[0x29]	2447667	1			T1	8009		T2	2487		T13	1844
valid_sources[0x2a]	4429371	1			T1	7926		T2	2559		T13	1719
valid_sources[0x2b]	1337857	1			T1	7958		T2	2608		T13	1740
valid_sources[0x2c]	1331713	1			T1	7796		T2	2564		T13	1741
valid_sources[0x2d]	1990765	1			T1	8039		T2	2563		T13	1837
valid_sources[0x2e]	1482789	1			T1	8156		T2	2421		T13	1774
valid_sources[0x2f]	1338835	1			T1	7914		T2	2675		T13	1801
valid_sources[0x30]	1336457	1			T1	8039		T2	2472		T13	1936
valid_sources[0x31]	1337205	1			T1	8025		T2	2697		T13	1699
valid_sources[0x32]	2692647	1			T1	8149		T2	2653		T13	1963
valid_sources[0x33]	1336310	1			T1	8048		T2	2534		T13	1831
valid_sources[0x34]	1336442	1			T1	8103		T2	2631		T13	1834
valid_sources[0x35]	1443897	1			T1	8002		T2	2626		T13	1890
valid_sources[0x36]	1328277	1			T1	7960		T2	2494		T13	1605
valid_sources[0x37]	2217296	1			T1	8252		T2	2701		T13	1732
valid_sources[0x38]	1395692	1			T1	8134		T2	2725		T13	1833
valid_sources[0x39]	3747357	1			T1	7936		T2	2666		T13	1727
valid_sources[0x3a]	1458646	1			T1	8078		T2	2485		T13	1721
valid_sources[0x3b]	1441351	1			T1	8089		T2	2631		T13	1837
valid_sources[0x3c]	1338785	1			T1	8059		T2	2598		T13	2023
valid_sources[0x3d]	1368483	1			T1	8136		T2	2492		T13	1769
valid_sources[0x3e]	1336728	1			T1	7991		T2	2487		T13	1773
valid_sources[0x3f]	1334787	1			T1	8130		T2	2621		T13	1775
valid_sources[0x40]	3786403	1			T1	8054		T2	2455		T13	1794
valid_sources[0x41]	1484629	1			T1	8227		T2	2696		T13	1914
valid_sources[0x42]	1333074	1			T1	8109		T2	2641		T13	1784
valid_sources[0x43]	1333310	1			T1	8093		T2	2577		T13	1681
valid_sources[0x44]	1331743	1			T1	8091		T2	2676		T13	1701
valid_sources[0x45]	1512287	1			T1	8001		T2	2620		T13	1776
valid_sources[0x46]	2268762	1			T1	7814		T2	2498		T13	1747
valid_sources[0x47]	2182556	1			T1	8155		T2	2312		T13	1736
valid_sources[0x48]	1793253	1			T1	8018		T2	2690		T13	1839
valid_sources[0x49]	2191417	1			T1	8076		T2	2737		T13	1895
valid_sources[0x4a]	1333141	1			T1	8047		T2	2580		T13	1797
valid_sources[0x4b]	2470894	1			T1	8093		T2	2496		T13	1857
valid_sources[0x4c]	2223573	1			T1	8095		T2	2836		T13	1823
valid_sources[0x4d]	1470908	1			T1	8070		T2	2656		T13	1809
valid_sources[0x4e]	1365601	1			T1	8103		T2	2676		T13	1925
valid_sources[0x4f]	2034517	1			T1	8046		T2	2481		T13	2017
valid_sources[0x50]	2461685	1			T1	8082		T2	2483		T13	1735
valid_sources[0x51]	1365013	1			T1	8003		T2	2584		T13	1818
valid_sources[0x52]	1332888	1			T1	8234		T2	2578		T13	1965
valid_sources[0x53]	1345577	1			T1	7962		T2	2672		T13	1742
valid_sources[0x54]	3495939	1			T1	8118		T2	2586		T13	1623
valid_sources[0x55]	1995096	1			T1	7968		T2	2656		T13	1775
valid_sources[0x56]	1329647	1			T1	8095		T2	2637		T13	1772
valid_sources[0x57]	1385952	1			T1	8263		T2	2578		T13	1814
valid_sources[0x58]	1337550	1			T1	8137		T2	2606		T13	1613
valid_sources[0x59]	3382168	1			T1	8130		T2	2537		T13	1665
valid_sources[0x5a]	1427651	1			T1	8058		T2	2598		T13	1826
valid_sources[0x5b]	1350889	1			T1	8142		T2	2680		T13	1879
valid_sources[0x5c]	1341839	1			T1	8065		T2	2395		T13	1814
valid_sources[0x5d]	1335585	1			T1	8188		T2	2565		T13	1893
valid_sources[0x5e]	1467705	1			T1	8285		T2	2435		T13	1768
valid_sources[0x5f]	1346179	1			T1	8074		T2	2702		T13	1850
valid_sources[0x60]	2063007	1			T1	7811		T2	2537		T13	1990
valid_sources[0x61]	1341333	1			T1	7956		T2	2643		T13	1832
valid_sources[0x62]	1365562	1			T1	7855		T2	2467		T13	1896
valid_sources[0x63]	2273344	1			T1	8145		T2	2377		T13	1873
valid_sources[0x64]	2488737	1			T1	7995		T2	2566		T13	1773
valid_sources[0x65]	1338228	1			T1	8277		T2	2653		T13	1860
valid_sources[0x66]	2266914	1			T1	8257		T2	2573		T13	1914
valid_sources[0x67]	1327169	1			T1	8155		T2	2495		T13	1849
valid_sources[0x68]	1337596	1			T1	8087		T2	2497		T13	1787
valid_sources[0x69]	1338685	1			T1	8189		T2	2589		T13	1913
valid_sources[0x6a]	1331717	1			T1	8068		T2	2576		T13	1780
valid_sources[0x6b]	1341214	1			T1	7890		T2	2594		T13	1743
valid_sources[0x6c]	3433545	1			T1	8130		T2	2470		T13	1836
valid_sources[0x6d]	1451064	1			T1	8129		T2	2515		T13	1768
valid_sources[0x6e]	3773235	1			T1	8026		T2	2581		T13	1894
valid_sources[0x6f]	1336933	1			T1	8091		T2	2530		T13	1607
valid_sources[0x70]	1338274	1			T1	8245		T2	2775		T13	2063
valid_sources[0x71]	3412951	1			T1	8144		T2	2594		T13	1834
valid_sources[0x72]	1351929	1			T1	7866		T2	2615		T13	1866
valid_sources[0x73]	1812333	1			T1	8261		T2	2596		T13	1813
valid_sources[0x74]	1341289	1			T1	7958		T2	2874		T13	1783
valid_sources[0x75]	1333684	1			T1	8145		T2	2608		T13	1636
valid_sources[0x76]	3371001	1			T1	8010		T2	2452		T13	1965
valid_sources[0x77]	1459692	1			T1	8177		T2	2646		T13	1758
valid_sources[0x78]	1330646	1			T1	7968		T2	2562		T13	1829
valid_sources[0x79]	1329282	1			T1	8340		T2	2495		T13	1817
valid_sources[0x7a]	1334086	1			T1	8146		T2	2714		T13	2021
valid_sources[0x7b]	1471424	1			T1	8015		T2	2482		T13	1882
valid_sources[0x7c]	1328531	1			T1	8045		T2	2357		T13	1746
valid_sources[0x7d]	2002488	1			T1	8012		T2	2539		T13	1905
valid_sources[0x7e]	1331700	1			T1	8053		T2	2702		T13	1843
valid_sources[0x7f]	2404861	1			T1	8152		T2	2674		T13	1939
valid_sources[0x80]	1330510	1			T1	8108		T2	2736		T13	1714

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87001835

1

T1

421418

T2

99427

T3

416392

values[0x0]

all_enables

biggest_size

60205609

1

T1

253731

T2

88147

T3

255566

values[0x1]

all_enables

biggest_size

51623596

1

T1

212348

T2

74237

T3

216333