Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253699633

1

T1

117787

T2

398225

T3

113277

full_word

198831773

1

T1

887497

T2

261811

T3

888291

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452531126	1			T1	206536		T2	660036		T3	202106
auto[TlIntgErrCmd]	88	1			T54	3		T110	2		T111	2
auto[TlIntgErrData]	79	1			T54	2		T110	3		T111	1
auto[TlIntgErrBoth]	113	1			T54	5		T110	5		T111	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239264979

1

T1

112139

T2

338299

T3

109650

auto[1]

213266427

1

T1

943976

T2

321737

T3

924556

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152262846	1			T1	699973		T2	238872		T3	680115
auto[TlIntgErrNone]	partial	auto[1]	101436527	1			T1	477897		T2	159353		T3	452657
auto[TlIntgErrNone]	full_word	auto[0]	87002008	1			T1	421418		T2	99427		T3	416392
auto[TlIntgErrNone]	full_word	auto[1]	111829745	1			T1	466079		T2	162384		T3	471899
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T54	1		T110	1		T111	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T54	2		T132	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T163	4		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T110	1		T165	1		-	-
auto[TlIntgErrData]	partial	auto[0]	30	1			T54	1		T110	2		T132	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T54	1		T110	1		T111	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T132	1		T166	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T161	2		T167	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T54	2		T110	1		T111	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T54	3		T110	2		T111	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T110	1		T111	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	1		T168	1		T167	2