Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2873	0	0
entropy_period_rd_A	2147483647	2098	0	0
intr_enable_rd_A	2147483647	2664	0	0
prefix_0_rd_A	2147483647	1922	0	0
prefix_10_rd_A	2147483647	1999	0	0
prefix_1_rd_A	2147483647	1987	0	0
prefix_2_rd_A	2147483647	1935	0	0
prefix_3_rd_A	2147483647	1917	0	0
prefix_4_rd_A	2147483647	2009	0	0
prefix_5_rd_A	2147483647	1974	0	0
prefix_6_rd_A	2147483647	1998	0	0
prefix_7_rd_A	2147483647	2010	0	0
prefix_8_rd_A	2147483647	1998	0	0
prefix_9_rd_A	2147483647	2048	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2873	0	0
T52	3610	100	0	0
T53	5305	64	0	0
T108	5810	134	0	0
T109	6539	7	0	0
T111	12705	2	0	0
T112	2529	122	0	0
T124	3443	4	0	0
T129	4398	5	0	0
T130	7185	9	0	0
T131	7774	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T94	12816	90	0	0
T95	9556	8	0	0
T111	12705	71	0	0
T129	4398	5	0	0
T130	7185	13	0	0
T131	7774	22	0	0
T132	12645	53	0	0
T142	49341	441	0	0
T143	6166	22	0	0
T144	2315	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2664	0	0
T94	12816	65	0	0
T95	9556	11	0	0
T111	12705	54	0	0
T120	1693	16	0	0
T129	4398	12	0	0
T131	7774	18	0	0
T132	12645	81	0	0
T142	49341	466	0	0
T143	6166	26	0	0
T144	2315	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1922	0	0
T94	12816	54	0	0
T95	9556	18	0	0
T107	5413	10	0	0
T111	12705	25	0	0
T129	4398	3	0	0
T130	7185	2	0	0
T131	7774	17	0	0
T132	12645	39	0	0
T142	49341	396	0	0
T143	6166	36	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1999	0	0
T94	12816	46	0	0
T95	9556	5	0	0
T111	12705	55	0	0
T129	4398	6	0	0
T130	7185	20	0	0
T131	7774	18	0	0
T132	12645	20	0	0
T142	49341	485	0	0
T143	6166	41	0	0
T144	2315	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1987	0	0
T94	12816	52	0	0
T95	9556	24	0	0
T111	12705	31	0	0
T129	4398	13	0	0
T130	7185	11	0	0
T131	7774	15	0	0
T132	12645	38	0	0
T142	49341	462	0	0
T143	6166	12	0	0
T144	2315	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935	0	0
T94	12816	67	0	0
T95	9556	20	0	0
T107	5413	29	0	0
T111	12705	39	0	0
T129	4398	16	0	0
T130	7185	5	0	0
T131	7774	31	0	0
T132	12645	43	0	0
T142	49341	475	0	0
T143	6166	17	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T94	12816	54	0	0
T95	9556	21	0	0
T111	12705	34	0	0
T129	4398	5	0	0
T130	7185	3	0	0
T131	7774	12	0	0
T132	12645	39	0	0
T142	49341	462	0	0
T143	6166	13	0	0
T144	2315	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2009	0	0
T94	12816	62	0	0
T95	9556	33	0	0
T111	12705	47	0	0
T129	4398	12	0	0
T130	7185	8	0	0
T131	7774	20	0	0
T132	12645	57	0	0
T142	49341	455	0	0
T143	6166	15	0	0
T144	2315	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T94	12816	77	0	0
T107	5413	27	0	0
T111	12705	52	0	0
T129	4398	5	0	0
T130	7185	20	0	0
T131	7774	12	0	0
T132	12645	35	0	0
T142	49341	476	0	0
T143	6166	35	0	0
T144	2315	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1998	0	0
T94	12816	47	0	0
T95	9556	18	0	0
T111	12705	51	0	0
T129	4398	4	0	0
T130	7185	5	0	0
T131	7774	11	0	0
T132	12645	28	0	0
T142	49341	431	0	0
T143	6166	14	0	0
T144	2315	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T94	12816	45	0	0
T95	9556	28	0	0
T111	12705	33	0	0
T129	4398	10	0	0
T130	7185	7	0	0
T131	7774	4	0	0
T132	12645	26	0	0
T142	49341	494	0	0
T143	6166	26	0	0
T144	2315	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1998	0	0
T94	12816	57	0	0
T95	9556	45	0	0
T111	12705	30	0	0
T129	4398	4	0	0
T130	7185	22	0	0
T131	7774	16	0	0
T132	12645	40	0	0
T142	49341	433	0	0
T143	6166	37	0	0
T144	2315	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T94	12816	63	0	0
T95	9556	53	0	0
T111	12705	44	0	0
T129	4398	2	0	0
T130	7185	2	0	0
T131	7774	7	0	0
T132	12645	50	0	0
T142	49341	437	0	0
T143	6166	32	0	0
T144	2315	4	0	0