SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 309497213 | 1 | T1 | 353246 | T2 | 657666 | T3 | 10952 | ||||
auto[1] | 145690619 | 1 | T1 | 145422 | T2 | 239292 | T3 | 99583 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 455187628 | 1 | T1 | 498668 | T2 | 896958 | T3 | 110535 | ||||
values[1] | 12 | 1 | T57 | 1 | T126 | 2 | T193 | 1 | ||||
values[2] | 4 | 1 | T57 | 1 | T126 | 1 | T127 | 1 | ||||
values[3] | 111 | 1 | T57 | 5 | T126 | 9 | T127 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 455187627 | 1 | T1 | 498668 | T2 | 896958 | T3 | 110535 | ||||
values[1] | 23 | 1 | T57 | 2 | T126 | 1 | T127 | 1 | ||||
values[2] | 7 | 1 | T57 | 2 | T145 | 1 | T194 | 1 | ||||
values[3] | 105 | 1 | T57 | 6 | T126 | 9 | T127 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 455187522 | 1 | T1 | 498668 | T2 | 896958 | T3 | 110535 | ||||
auto[TlIntgErrCmd] | 105 | 1 | T57 | 4 | T126 | 8 | T127 | 4 | ||||
auto[TlIntgErrData] | 106 | 1 | T57 | 10 | T126 | 7 | T127 | 5 | ||||
auto[TlIntgErrBoth] | 99 | 1 | T57 | 6 | T126 | 5 | T127 | 11 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |