Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254660090

1

T1

297341

T2

538017

T3

7662

full_word

200527742

1

T1

201327

T2

358941

T3

102873

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	455187522	1			T1	498668		T2	896958		T3	110535
auto[TlIntgErrCmd]	105	1			T57	4		T126	8		T127	4
auto[TlIntgErrData]	106	1			T57	10		T126	7		T127	5
auto[TlIntgErrBoth]	99	1			T57	6		T126	5		T127	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240240876

1

T1

263128

T2

457915

T3

30280

auto[1]

214946956

1

T1

235540

T2

439043

T3

80255

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152711088	1			T1	174823		T2	326475		T3	6450
auto[TlIntgErrNone]	partial	auto[1]	101948719	1			T1	122518		T2	211542		T3	1212
auto[TlIntgErrNone]	full_word	auto[0]	87529648	1			T1	88305		T2	131440		T3	23830
auto[TlIntgErrNone]	full_word	auto[1]	112998067	1			T1	113022		T2	227501		T3	79043
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T57	2		T126	3		T145	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T57	2		T126	4		T127	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T194	1		T195	3		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T126	1		T196	1		T197	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T57	5		T126	5		T127	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T57	3		T126	2		T145	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T57	1		T127	1		T179	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T57	1		T127	1		T198	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T57	2		T126	1		T127	5
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T57	2		T126	3		T127	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T57	1		T145	1		T193	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T57	1		T126	1		T127	2