Module Definition
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Module : kmac_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.90 100.00 99.60 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.90 100.00 99.60 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.90 100.00 99.60 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.99 99.19 97.03 100.00 98.72 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.24 96.27 93.33 100.00 100.00 93.85 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault_err 100.00 100.00
u_alert_test_recov_operation_err 100.00 100.00
u_cfg_regwen 100.00 100.00
u_cfg_shadowed0_qe 100.00 100.00 100.00
u_cfg_shadowed_en_unsupported_modestrength 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_entropy_fast_process 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_entropy_mode 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_entropy_ready 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_kmac_en 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_kstrength 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_mode 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_msg_endianness 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_msg_mask 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_sideload 98.66 100.00 94.64 100.00 100.00
u_cfg_shadowed_state_endianness 98.66 100.00 94.64 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_cmd_cmd 100.00 100.00
u_cmd_entropy_req 100.00 100.00
u_cmd_err_processed 100.00 100.00
u_cmd_hash_cnt_clr 100.00 100.00
u_entropy_period_prescaler 100.00 100.00 100.00 100.00
u_entropy_period_wait_timer 100.00 100.00 100.00 100.00
u_entropy_refresh_hash_cnt 58.89 66.67 50.00 60.00
u_entropy_refresh_threshold_shadowed 98.66 100.00 94.64 100.00 100.00
u_entropy_seed 100.00 100.00
u_err_code 100.00 100.00 100.00 100.00
u_intr_enable_fifo_empty 100.00 100.00 100.00 100.00
u_intr_enable_kmac_done 100.00 100.00 100.00 100.00
u_intr_enable_kmac_err 100.00 100.00 100.00 100.00
u_intr_state_fifo_empty 62.59 77.78 50.00 60.00
u_intr_state_kmac_done 100.00 100.00 100.00 100.00
u_intr_state_kmac_err 100.00 100.00 100.00 100.00
u_intr_test_fifo_empty 100.00 100.00
u_intr_test_kmac_done 100.00 100.00
u_intr_test_kmac_err 100.00 100.00
u_key_len 100.00 100.00 100.00 100.00
u_key_share0_0 100.00 100.00
u_key_share0_1 100.00 100.00
u_key_share0_10 100.00 100.00
u_key_share0_11 100.00 100.00
u_key_share0_12 100.00 100.00
u_key_share0_13 100.00 100.00
u_key_share0_14 100.00 100.00
u_key_share0_15 100.00 100.00
u_key_share0_2 100.00 100.00
u_key_share0_3 100.00 100.00
u_key_share0_4 100.00 100.00
u_key_share0_5 100.00 100.00
u_key_share0_6 100.00 100.00
u_key_share0_7 100.00 100.00
u_key_share0_8 100.00 100.00
u_key_share0_9 100.00 100.00
u_key_share1_0 100.00 100.00
u_key_share1_1 100.00 100.00
u_key_share1_10 100.00 100.00
u_key_share1_11 100.00 100.00
u_key_share1_12 100.00 100.00
u_key_share1_13 100.00 100.00
u_key_share1_14 100.00 100.00
u_key_share1_15 100.00 100.00
u_key_share1_2 100.00 100.00
u_key_share1_3 100.00 100.00
u_key_share1_4 100.00 100.00
u_key_share1_5 100.00 100.00
u_key_share1_6 100.00 100.00
u_key_share1_7 100.00 100.00
u_key_share1_8 100.00 100.00
u_key_share1_9 100.00 100.00
u_prefix_0 100.00 100.00 100.00 100.00
u_prefix_1 100.00 100.00 100.00 100.00
u_prefix_10 100.00 100.00 100.00 100.00
u_prefix_2 100.00 100.00 100.00 100.00
u_prefix_3 100.00 100.00 100.00 100.00
u_prefix_4 100.00 100.00 100.00 100.00
u_prefix_5 100.00 100.00 100.00 100.00
u_prefix_6 100.00 100.00 100.00 100.00
u_prefix_7 100.00 100.00 100.00 100.00
u_prefix_8 100.00 100.00 100.00 100.00
u_prefix_9 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_socket 93.69 96.05 89.53 89.19 100.00
u_status_alert_fatal_fault 100.00 100.00
u_status_alert_recov_ctrl_update_err 100.00 100.00
u_status_fifo_depth 100.00 100.00
u_status_fifo_empty 100.00 100.00
u_status_fifo_full 100.00 100.00
u_status_sha3_absorb 100.00 100.00
u_status_sha3_idle 100.00 100.00
u_status_sha3_squeeze 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : kmac_reg_top
Line No.TotalCoveredPercent
TOTAL499499100.00
ALWAYS7744100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
ALWAYS13633100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN56211100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN59411100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN63111100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN77411100.00
CONT_ASSIGN81111100.00
CONT_ASSIGN84811100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN95911100.00
CONT_ASSIGN99611100.00
CONT_ASSIGN103311100.00
CONT_ASSIGN107011100.00
CONT_ASSIGN107611100.00
CONT_ASSIGN109111100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112311100.00
CONT_ASSIGN113911100.00
CONT_ASSIGN126711100.00
CONT_ASSIGN135411100.00
CONT_ASSIGN139511100.00
CONT_ASSIGN140911100.00
CONT_ASSIGN141611100.00
CONT_ASSIGN141911100.00
CONT_ASSIGN143311100.00
CONT_ASSIGN144011100.00
CONT_ASSIGN144311100.00
CONT_ASSIGN145711100.00
CONT_ASSIGN146411100.00
CONT_ASSIGN146711100.00
CONT_ASSIGN148111100.00
CONT_ASSIGN148811100.00
CONT_ASSIGN149111100.00
CONT_ASSIGN150511100.00
CONT_ASSIGN151211100.00
CONT_ASSIGN151511100.00
CONT_ASSIGN152911100.00
CONT_ASSIGN153611100.00
CONT_ASSIGN153911100.00
CONT_ASSIGN155311100.00
CONT_ASSIGN156011100.00
CONT_ASSIGN156311100.00
CONT_ASSIGN157711100.00
CONT_ASSIGN158411100.00
CONT_ASSIGN158711100.00
CONT_ASSIGN160111100.00
CONT_ASSIGN160811100.00
CONT_ASSIGN161111100.00
CONT_ASSIGN162511100.00
CONT_ASSIGN163211100.00
CONT_ASSIGN163511100.00
CONT_ASSIGN164911100.00
CONT_ASSIGN165611100.00
CONT_ASSIGN165911100.00
CONT_ASSIGN167311100.00
CONT_ASSIGN168011100.00
CONT_ASSIGN168311100.00
CONT_ASSIGN169711100.00
CONT_ASSIGN170411100.00
CONT_ASSIGN170711100.00
CONT_ASSIGN172111100.00
CONT_ASSIGN172811100.00
CONT_ASSIGN173111100.00
CONT_ASSIGN174511100.00
CONT_ASSIGN175211100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN176911100.00
CONT_ASSIGN177611100.00
CONT_ASSIGN177911100.00
CONT_ASSIGN179311100.00
CONT_ASSIGN180011100.00
CONT_ASSIGN180311100.00
CONT_ASSIGN181711100.00
CONT_ASSIGN182411100.00
CONT_ASSIGN182711100.00
CONT_ASSIGN184111100.00
CONT_ASSIGN184811100.00
CONT_ASSIGN185111100.00
CONT_ASSIGN186511100.00
CONT_ASSIGN187211100.00
CONT_ASSIGN187511100.00
CONT_ASSIGN188911100.00
CONT_ASSIGN189611100.00
CONT_ASSIGN189911100.00
CONT_ASSIGN191311100.00
CONT_ASSIGN192011100.00
CONT_ASSIGN192311100.00
CONT_ASSIGN193711100.00
CONT_ASSIGN194411100.00
CONT_ASSIGN194711100.00
CONT_ASSIGN196111100.00
CONT_ASSIGN196811100.00
CONT_ASSIGN197111100.00
CONT_ASSIGN198511100.00
CONT_ASSIGN199211100.00
CONT_ASSIGN199511100.00
CONT_ASSIGN200911100.00
CONT_ASSIGN201611100.00
CONT_ASSIGN201911100.00
CONT_ASSIGN203311100.00
CONT_ASSIGN204011100.00
CONT_ASSIGN204311100.00
CONT_ASSIGN205711100.00
CONT_ASSIGN206411100.00
CONT_ASSIGN206711100.00
CONT_ASSIGN208111100.00
CONT_ASSIGN208811100.00
CONT_ASSIGN209111100.00
CONT_ASSIGN210511100.00
CONT_ASSIGN211211100.00
CONT_ASSIGN211511100.00
CONT_ASSIGN212911100.00
CONT_ASSIGN213611100.00
CONT_ASSIGN213911100.00
CONT_ASSIGN215311100.00
CONT_ASSIGN216011100.00
CONT_ASSIGN216311100.00
CONT_ASSIGN217711100.00
CONT_ASSIGN218311100.00
CONT_ASSIGN221511100.00
CONT_ASSIGN224711100.00
CONT_ASSIGN227911100.00
CONT_ASSIGN231111100.00
CONT_ASSIGN234311100.00
CONT_ASSIGN237511100.00
CONT_ASSIGN240711100.00
CONT_ASSIGN243911100.00
CONT_ASSIGN247111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN253511100.00
ALWAYS25945858100.00
CONT_ASSIGN265411100.00
ALWAYS265811100.00
CONT_ASSIGN271911100.00
CONT_ASSIGN272111100.00
CONT_ASSIGN272311100.00
CONT_ASSIGN272411100.00
CONT_ASSIGN272611100.00
CONT_ASSIGN272811100.00
CONT_ASSIGN273011100.00
CONT_ASSIGN273111100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273511100.00
CONT_ASSIGN273711100.00
CONT_ASSIGN273811100.00
CONT_ASSIGN274011100.00
CONT_ASSIGN274211100.00
CONT_ASSIGN274311100.00
CONT_ASSIGN274411100.00
CONT_ASSIGN274511100.00
CONT_ASSIGN274711100.00
CONT_ASSIGN274911100.00
CONT_ASSIGN275111100.00
CONT_ASSIGN275311100.00
CONT_ASSIGN275511100.00
CONT_ASSIGN275711100.00
CONT_ASSIGN275911100.00
CONT_ASSIGN276111100.00
CONT_ASSIGN276311100.00
CONT_ASSIGN276511100.00
CONT_ASSIGN276711100.00
CONT_ASSIGN276811100.00
CONT_ASSIGN277011100.00
CONT_ASSIGN277211100.00
CONT_ASSIGN277411100.00
CONT_ASSIGN277611100.00
CONT_ASSIGN277711100.00
CONT_ASSIGN277811100.00
CONT_ASSIGN278011100.00
CONT_ASSIGN278211100.00
CONT_ASSIGN278311100.00
CONT_ASSIGN278411100.00
CONT_ASSIGN278611100.00
CONT_ASSIGN278711100.00
CONT_ASSIGN278911100.00
CONT_ASSIGN279011100.00
CONT_ASSIGN279211100.00
CONT_ASSIGN279311100.00
CONT_ASSIGN279511100.00
CONT_ASSIGN279611100.00
CONT_ASSIGN279811100.00
CONT_ASSIGN279911100.00
CONT_ASSIGN280111100.00
CONT_ASSIGN280211100.00
CONT_ASSIGN280411100.00
CONT_ASSIGN280511100.00
CONT_ASSIGN280711100.00
CONT_ASSIGN280811100.00
CONT_ASSIGN281011100.00
CONT_ASSIGN281111100.00
CONT_ASSIGN281311100.00
CONT_ASSIGN281411100.00
CONT_ASSIGN281611100.00
CONT_ASSIGN281711100.00
CONT_ASSIGN281911100.00
CONT_ASSIGN282011100.00
CONT_ASSIGN282211100.00
CONT_ASSIGN282311100.00
CONT_ASSIGN282511100.00
CONT_ASSIGN282611100.00
CONT_ASSIGN282811100.00
CONT_ASSIGN282911100.00
CONT_ASSIGN283111100.00
CONT_ASSIGN283211100.00
CONT_ASSIGN283411100.00
CONT_ASSIGN283511100.00
CONT_ASSIGN283711100.00
CONT_ASSIGN283811100.00
CONT_ASSIGN284011100.00
CONT_ASSIGN284111100.00
CONT_ASSIGN284311100.00
CONT_ASSIGN284411100.00
CONT_ASSIGN284611100.00
CONT_ASSIGN284711100.00
CONT_ASSIGN284911100.00
CONT_ASSIGN285011100.00
CONT_ASSIGN285211100.00
CONT_ASSIGN285311100.00
CONT_ASSIGN285511100.00
CONT_ASSIGN285611100.00
CONT_ASSIGN285811100.00
CONT_ASSIGN285911100.00
CONT_ASSIGN286111100.00
CONT_ASSIGN286211100.00
CONT_ASSIGN286411100.00
CONT_ASSIGN286511100.00
CONT_ASSIGN286711100.00
CONT_ASSIGN286811100.00
CONT_ASSIGN287011100.00
CONT_ASSIGN287111100.00
CONT_ASSIGN287311100.00
CONT_ASSIGN287411100.00
CONT_ASSIGN287611100.00
CONT_ASSIGN287711100.00
CONT_ASSIGN287911100.00
CONT_ASSIGN288011100.00
CONT_ASSIGN288211100.00
CONT_ASSIGN288311100.00
CONT_ASSIGN288511100.00
CONT_ASSIGN288611100.00
CONT_ASSIGN288811100.00
CONT_ASSIGN288911100.00
CONT_ASSIGN289111100.00
CONT_ASSIGN289211100.00
CONT_ASSIGN289411100.00
CONT_ASSIGN289511100.00
CONT_ASSIGN289711100.00
CONT_ASSIGN289811100.00
CONT_ASSIGN290011100.00
CONT_ASSIGN290111100.00
CONT_ASSIGN290311100.00
CONT_ASSIGN290411100.00
CONT_ASSIGN290611100.00
CONT_ASSIGN290711100.00
CONT_ASSIGN290911100.00
CONT_ASSIGN291011100.00
CONT_ASSIGN291211100.00
CONT_ASSIGN291311100.00
CONT_ASSIGN291511100.00
CONT_ASSIGN291611100.00
CONT_ASSIGN291811100.00
CONT_ASSIGN291911100.00
CONT_ASSIGN292111100.00
ALWAYS29255858100.00
ALWAYS29878787100.00
ALWAYS325633100.00
ALWAYS326433100.00
CONT_ASSIGN327211100.00
CONT_ASSIGN327511100.00
CONT_ASSIGN328911100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
77 1 1
78 1 1
79 1 1
80 1 1
MISSING_ELSE
86 1 1
104 1 1
105 1 1
107 1 1
108 1 1
109 1 1
110 1 1
136 1 1
143 1 1
144 1 1
MISSING_ELSE
174 1 1
175 1 1
547 1 1
562 1 1
578 1 1
594 1 1
600 1 1
615 1 1
631 1 1
664 1 1
700 1 1
737 1 1
774 1 1
811 1 1
848 1 1
885 1 1
922 1 1
959 1 1
996 1 1
1033 1 1
1070 1 1
1076 1 1
1091 1 1
1107 1 1
1123 1 1
1139 1 1
1267 1 1
1354 1 1
1395 1 1
1409 1 1
1416 1 1
1419 1 1
1433 1 1
1440 1 1
1443 1 1
1457 1 1
1464 1 1
1467 1 1
1481 1 1
1488 1 1
1491 1 1
1505 1 1
1512 1 1
1515 1 1
1529 1 1
1536 1 1
1539 1 1
1553 1 1
1560 1 1
1563 1 1
1577 1 1
1584 1 1
1587 1 1
1601 1 1
1608 1 1
1611 1 1
1625 1 1
1632 1 1
1635 1 1
1649 1 1
1656 1 1
1659 1 1
1673 1 1
1680 1 1
1683 1 1
1697 1 1
1704 1 1
1707 1 1
1721 1 1
1728 1 1
1731 1 1
1745 1 1
1752 1 1
1755 1 1
1769 1 1
1776 1 1
1779 1 1
1793 1 1
1800 1 1
1803 1 1
1817 1 1
1824 1 1
1827 1 1
1841 1 1
1848 1 1
1851 1 1
1865 1 1
1872 1 1
1875 1 1
1889 1 1
1896 1 1
1899 1 1
1913 1 1
1920 1 1
1923 1 1
1937 1 1
1944 1 1
1947 1 1
1961 1 1
1968 1 1
1971 1 1
1985 1 1
1992 1 1
1995 1 1
2009 1 1
2016 1 1
2019 1 1
2033 1 1
2040 1 1
2043 1 1
2057 1 1
2064 1 1
2067 1 1
2081 1 1
2088 1 1
2091 1 1
2105 1 1
2112 1 1
2115 1 1
2129 1 1
2136 1 1
2139 1 1
2153 1 1
2160 1 1
2163 1 1
2177 1 1
2183 1 1
2215 1 1
2247 1 1
2279 1 1
2311 1 1
2343 1 1
2375 1 1
2407 1 1
2439 1 1
2471 1 1
2503 1 1
2535 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2599 1 1
2600 1 1
2601 1 1
2602 1 1
2603 1 1
2604 1 1
2605 1 1
2606 1 1
2607 1 1
2608 1 1
2609 1 1
2610 1 1
2611 1 1
2612 1 1
2613 1 1
2614 1 1
2615 1 1
2616 1 1
2617 1 1
2618 1 1
2619 1 1
2620 1 1
2621 1 1
2622 1 1
2623 1 1
2624 1 1
2625 1 1
2626 1 1
2627 1 1
2628 1 1
2629 1 1
2630 1 1
2631 1 1
2632 1 1
2633 1 1
2634 1 1
2635 1 1
2636 1 1
2637 1 1
2638 1 1
2639 1 1
2640 1 1
2641 1 1
2642 1 1
2643 1 1
2644 1 1
2645 1 1
2646 1 1
2647 1 1
2648 1 1
2649 1 1
2650 1 1
2651 1 1
2654 1 1
2658 1 1
2719 1 1
2721 1 1
2723 1 1
2724 1 1
2726 1 1
2728 1 1
2730 1 1
2731 1 1
2733 1 1
2735 1 1
2737 1 1
2738 1 1
2740 1 1
2742 1 1
2743 1 1
2744 1 1
2745 1 1
2747 1 1
2749 1 1
2751 1 1
2753 1 1
2755 1 1
2757 1 1
2759 1 1
2761 1 1
2763 1 1
2765 1 1
2767 1 1
2768 1 1
2770 1 1
2772 1 1
2774 1 1
2776 1 1
2777 1 1
2778 1 1
2780 1 1
2782 1 1
2783 1 1
2784 1 1
2786 1 1
2787 1 1
2789 1 1
2790 1 1
2792 1 1
2793 1 1
2795 1 1
2796 1 1
2798 1 1
2799 1 1
2801 1 1
2802 1 1
2804 1 1
2805 1 1
2807 1 1
2808 1 1
2810 1 1
2811 1 1
2813 1 1
2814 1 1
2816 1 1
2817 1 1
2819 1 1
2820 1 1
2822 1 1
2823 1 1
2825 1 1
2826 1 1
2828 1 1
2829 1 1
2831 1 1
2832 1 1
2834 1 1
2835 1 1
2837 1 1
2838 1 1
2840 1 1
2841 1 1
2843 1 1
2844 1 1
2846 1 1
2847 1 1
2849 1 1
2850 1 1
2852 1 1
2853 1 1
2855 1 1
2856 1 1
2858 1 1
2859 1 1
2861 1 1
2862 1 1
2864 1 1
2865 1 1
2867 1 1
2868 1 1
2870 1 1
2871 1 1
2873 1 1
2874 1 1
2876 1 1
2877 1 1
2879 1 1
2880 1 1
2882 1 1
2883 1 1
2885 1 1
2886 1 1
2888 1 1
2889 1 1
2891 1 1
2892 1 1
2894 1 1
2895 1 1
2897 1 1
2898 1 1
2900 1 1
2901 1 1
2903 1 1
2904 1 1
2906 1 1
2907 1 1
2909 1 1
2910 1 1
2912 1 1
2913 1 1
2915 1 1
2916 1 1
2918 1 1
2919 1 1
2921 1 1
2925 1 1
2926 1 1
2927 1 1
2928 1 1
2929 1 1
2930 1 1
2931 1 1
2932 1 1
2933 1 1
2934 1 1
2935 1 1
2936 1 1
2937 1 1
2938 1 1
2939 1 1
2940 1 1
2941 1 1
2942 1 1
2943 1 1
2944 1 1
2945 1 1
2946 1 1
2947 1 1
2948 1 1
2949 1 1
2950 1 1
2951 1 1
2952 1 1
2953 1 1
2954 1 1
2955 1 1
2956 1 1
2957 1 1
2958 1 1
2959 1 1
2960 1 1
2961 1 1
2962 1 1
2963 1 1
2964 1 1
2965 1 1
2966 1 1
2967 1 1
2968 1 1
2969 1 1
2970 1 1
2971 1 1
2972 1 1
2973 1 1
2974 1 1
2975 1 1
2976 1 1
2977 1 1
2978 1 1
2979 1 1
2980 1 1
2981 1 1
2982 1 1
2987 1 1
2988 1 1
2990 1 1
2991 1 1
2992 1 1
2996 1 1
2997 1 1
2998 1 1
3002 1 1
3003 1 1
3004 1 1
3008 1 1
3009 1 1
3013 1 1
3017 1 1
3018 1 1
3019 1 1
3020 1 1
3021 1 1
3022 1 1
3023 1 1
3024 1 1
3025 1 1
3026 1 1
3027 1 1
3031 1 1
3032 1 1
3033 1 1
3034 1 1
3038 1 1
3039 1 1
3040 1 1
3041 1 1
3042 1 1
3043 1 1
3044 1 1
3045 1 1
3049 1 1
3050 1 1
3054 1 1
3058 1 1
3062 1 1
3066 1 1
3070 1 1
3074 1 1
3078 1 1
3082 1 1
3086 1 1
3090 1 1
3094 1 1
3098 1 1
3102 1 1
3106 1 1
3110 1 1
3114 1 1
3118 1 1
3122 1 1
3126 1 1
3130 1 1
3134 1 1
3138 1 1
3142 1 1
3146 1 1
3150 1 1
3154 1 1
3158 1 1
3162 1 1
3166 1 1
3170 1 1
3174 1 1
3178 1 1
3182 1 1
3186 1 1
3190 1 1
3194 1 1
3198 1 1
3202 1 1
3206 1 1
3210 1 1
3214 1 1
3218 1 1
3222 1 1
3226 1 1
3230 1 1
3234 1 1
3238 1 1
3242 1 1
3256 1 1
3257 1 1
3259 1 1
3264 1 1
3265 1 1
3267 1 1
3272 1 1
3275 1 1
3289 1 1
3305 1 1
3313 1 1
3314 1 1


Cond Coverage for Module : kmac_reg_top
TotalCoveredPercent
Conditions74173899.60
Logical74173899.60
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
67-2658100.00
2658-327299.10

Branch Coverage for Module : kmac_reg_top
Line No.TotalCoveredPercent
Branches 72 72 100.00
TERNARY 2654 2 2 100.00
IF 77 3 3 100.00
TERNARY 136 3 3 100.00
IF 143 2 2 100.00
CASE 2988 58 58 100.00
IF 3256 2 2 100.00
IF 3264 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2654 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 77 if ((!rst_ni)) -2-: 79 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T11,T12
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 136 ((tl_i.a_address[(AW - 1):0] inside {[1024:1535]})) ? -2-: 136 ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 143 if (intg_err)

Branches:
-1-StatusTests
1 Covered T57,T126,T127
0 Covered T1,T2,T3


LineNo. Expression -1-: 2988 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
addr_hit[38] Covered T1,T2,T3
addr_hit[39] Covered T1,T2,T3
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
addr_hit[43] Covered T1,T2,T3
addr_hit[44] Covered T1,T2,T3
addr_hit[45] Covered T1,T2,T3
addr_hit[46] Covered T1,T2,T3
addr_hit[47] Covered T1,T2,T3
addr_hit[48] Covered T1,T2,T3
addr_hit[49] Covered T1,T2,T3
addr_hit[50] Covered T1,T2,T3
addr_hit[51] Covered T1,T2,T3
addr_hit[52] Covered T1,T2,T3
addr_hit[53] Covered T1,T2,T3
addr_hit[54] Covered T1,T2,T3
addr_hit[55] Covered T1,T2,T3
addr_hit[56] Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 3256 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 3264 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : kmac_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 2147483647 309365408 0 0
reAfterRv 2147483647 309365408 0 0
rePulse 2147483647 203224752 0 0
wePulse 2147483647 106140656 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 309365408 0 0
T1 338713 353246 0 0
T2 183456 657666 0 0
T3 744243 10952 0 0
T13 430419 139795 0 0
T14 954593 67776 0 0
T15 272202 48716 0 0
T16 616283 641624 0 0
T17 15153 1060 0 0
T18 130828 969 0 0
T19 221538 170735 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 309365408 0 0
T1 338713 353246 0 0
T2 183456 657666 0 0
T3 744243 10952 0 0
T13 430419 139795 0 0
T14 954593 67776 0 0
T15 272202 48716 0 0
T16 616283 641624 0 0
T17 15153 1060 0 0
T18 130828 969 0 0
T19 221538 170735 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 203224752 0 0
T1 338713 233485 0 0
T2 183456 435685 0 0
T3 744243 7078 0 0
T13 430419 918077 0 0
T14 954593 41545 0 0
T15 272202 30913 0 0
T16 616283 425113 0 0
T17 15153 674 0 0
T18 130828 175 0 0
T19 221538 112165 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 106140656 0 0
T1 338713 119761 0 0
T2 183456 221981 0 0
T3 744243 3874 0 0
T13 430419 479876 0 0
T14 954593 26231 0 0
T15 272202 17803 0 0
T16 616283 216511 0 0
T17 15153 386 0 0
T18 130828 794 0 0
T19 221538 585702 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%