Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	46470	0	0
entropy_period_rd_A	2147483647	2158	0	0
intr_enable_rd_A	2147483647	2801	0	0
prefix_0_rd_A	2147483647	1847	0	0
prefix_10_rd_A	2147483647	1669	0	0
prefix_1_rd_A	2147483647	1657	0	0
prefix_2_rd_A	2147483647	1714	0	0
prefix_3_rd_A	2147483647	1817	0	0
prefix_4_rd_A	2147483647	1649	0	0
prefix_5_rd_A	2147483647	1664	0	0
prefix_6_rd_A	2147483647	1818	0	0
prefix_7_rd_A	2147483647	1742	0	0
prefix_8_rd_A	2147483647	1684	0	0
prefix_9_rd_A	2147483647	1666	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46470	0	0
T56	329628	43931	0	0
T57	0	2	0	0
T58	0	105	0	0
T65	3941	0	0	0
T125	0	3	0	0
T126	0	1	0	0
T127	0	4	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	1	0	0
T147	610481	0	0	0
T148	743802	0	0	0
T149	125112	0	0	0
T150	562409	0	0	0
T151	469218	0	0	0
T152	133870	0	0	0
T153	154847	0	0	0
T154	97850	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2158	0	0
T57	22920	137	0	0
T109	5414	16	0	0
T115	6607	36	0	0
T142	4093	8	0	0
T166	6538	49	0	0
T167	52001	454	0	0
T168	2748	6	0	0
T169	2391	7	0	0
T170	2182	2	0	0
T171	4222	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2801	0	0
T57	22920	184	0	0
T109	5414	37	0	0
T115	6607	14	0	0
T142	4093	26	0	0
T166	6538	26	0	0
T172	1624	15	0	0
T173	2159	11	0	0
T174	1245	8	0	0
T175	1522	15	0	0
T176	818	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T57	22920	81	0	0
T109	5414	14	0	0
T115	6607	19	0	0
T142	4093	12	0	0
T166	6538	30	0	0
T167	52001	480	0	0
T168	2748	3	0	0
T169	2391	2	0	0
T170	2182	2	0	0
T177	10075	39	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1669	0	0
T57	22920	84	0	0
T109	5414	29	0	0
T115	6607	17	0	0
T142	4093	16	0	0
T166	6538	8	0	0
T167	52001	408	0	0
T168	2748	12	0	0
T169	2391	3	0	0
T170	2182	5	0	0
T171	4222	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1657	0	0
T57	22920	75	0	0
T109	5414	18	0	0
T115	6607	12	0	0
T142	4093	6	0	0
T166	6538	11	0	0
T167	52001	420	0	0
T168	2748	8	0	0
T169	2391	5	0	0
T171	4222	9	0	0
T177	10075	34	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1714	0	0
T57	22920	83	0	0
T109	5414	7	0	0
T115	6607	23	0	0
T142	4093	5	0	0
T166	6538	15	0	0
T167	52001	445	0	0
T168	2748	11	0	0
T169	2391	3	0	0
T171	4222	7	0	0
T177	10075	27	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1817	0	0
T57	22920	68	0	0
T109	5414	8	0	0
T115	6607	30	0	0
T142	4093	8	0	0
T166	6538	47	0	0
T167	52001	412	0	0
T168	2748	9	0	0
T169	2391	4	0	0
T170	2182	3	0	0
T171	4222	7	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1649	0	0
T57	22920	89	0	0
T109	5414	4	0	0
T115	6607	11	0	0
T142	4093	5	0	0
T166	6538	16	0	0
T167	52001	443	0	0
T168	2748	10	0	0
T169	2391	6	0	0
T170	2182	4	0	0
T171	4222	17	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T57	22920	84	0	0
T109	5414	20	0	0
T115	6607	19	0	0
T142	4093	5	0	0
T166	6538	17	0	0
T167	52001	419	0	0
T168	2748	11	0	0
T169	2391	9	0	0
T170	2182	1	0	0
T171	4222	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1818	0	0
T57	22920	97	0	0
T109	5414	8	0	0
T115	6607	12	0	0
T142	4093	5	0	0
T166	6538	36	0	0
T167	52001	357	0	0
T168	2748	9	0	0
T170	2182	2	0	0
T171	4222	5	0	0
T177	10075	50	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1742	0	0
T57	22920	89	0	0
T115	6607	11	0	0
T142	4093	1	0	0
T166	6538	47	0	0
T167	52001	428	0	0
T168	2748	4	0	0
T171	4222	3	0	0
T177	10075	17	0	0
T178	1612	1	0	0
T179	45452	53	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T57	22920	77	0	0
T109	5414	17	0	0
T115	6607	5	0	0
T142	4093	11	0	0
T166	6538	9	0	0
T167	52001	351	0	0
T168	2748	6	0	0
T169	2391	3	0	0
T171	4222	9	0	0
T177	10075	22	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1666	0	0
T57	22920	77	0	0
T109	5414	12	0	0
T115	6607	34	0	0
T142	4093	11	0	0
T166	6538	27	0	0
T167	52001	436	0	0
T168	2748	4	0	0
T169	2391	6	0	0
T170	2182	4	0	0
T171	4222	1	0	0