Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_msgfifo.u_sram_byte	100.00	100.00					100.00
tb.dut.u_staterd.u_tlul_adapter.u_sram_byte	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.43	98.55	77.78			80.77	84.62	u_tlul_adapter_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	98.61	82.46			92.31	100.00	u_tlul_adapter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
702	1	1
703	1	1
704	1	1
710		unreachable
716		unreachable
717		unreachable

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	2044	2044	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	2044	2044	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T13	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
702	1	1
703	1	1
704	1	1
710		unreachable
716		unreachable
717		unreachable

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1022	1022	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
702	1	1
703	1	1
704	1	1
710		unreachable
716		unreachable
717		unreachable

---

Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1022	1022	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0