Module Definition
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Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter_msgfifo.u_sram_byte 100.00 100.00 100.00
tb.dut.u_staterd.u_tlul_adapter.u_sram_byte 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.43 98.55 77.78 80.77 84.62 u_tlul_adapter_msgfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 98.61 82.46 92.31 100.00 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Module : tlul_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 2044 2044 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 2044 2044 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Instance : tb.dut.u_tlul_adapter_msgfifo.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1022 1022 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Instance : tb.dut.u_staterd.u_tlul_adapter.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1022 1022 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%