Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	250006378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

195771681

1

T1

120020

T2

888407

T3

887328

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	235500332	1			T1	147407		T2	110534		T3	111737
values[0x0]	101041230	1			T1	61081		T2	448845		T3	453333
values[0x1]	109236497	1			T1	65750		T2	485357		T3	492045

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	194918398	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

250859661

1

T1

153808

T2

114032

T3

114636

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1289470	1			T1	115		T2	8336		T13	125
valid_sources[0x01]	1285958	1			T1	102		T2	7912		T13	136
valid_sources[0x02]	2471753	1			T1	106		T2	7895		T13	148
valid_sources[0x03]	1303773	1			T1	111		T2	7967		T13	150
valid_sources[0x04]	1288289	1			T1	108		T2	8100		T13	151
valid_sources[0x05]	1404445	1			T1	109		T2	8184		T13	144
valid_sources[0x06]	1288645	1			T1	110		T2	7836		T13	147
valid_sources[0x07]	1283072	1			T1	126		T2	7989		T13	126
valid_sources[0x08]	1373259	1			T1	115		T2	7854		T13	156
valid_sources[0x09]	1291589	1			T1	106		T2	8268		T13	148
valid_sources[0x0a]	1991595	1			T1	102		T2	8250		T13	145
valid_sources[0x0b]	1287128	1			T1	103		T2	8126		T13	149
valid_sources[0x0c]	4193192	1			T1	103		T2	7807		T13	140
valid_sources[0x0d]	1950562	1			T1	115		T2	7920		T13	149
valid_sources[0x0e]	1331888	1			T1	153		T2	7952		T13	150
valid_sources[0x0f]	1285257	1			T1	131		T2	8213		T13	146
valid_sources[0x10]	2131844	1			T1	117		T2	8126		T13	140
valid_sources[0x11]	1751377	1			T1	112		T2	7979		T13	136
valid_sources[0x12]	1282940	1			T1	108		T2	8056		T13	124
valid_sources[0x13]	1961553	1			T1	119		T2	8261		T13	140
valid_sources[0x14]	1286896	1			T1	115		T2	7953		T13	140
valid_sources[0x15]	1299565	1			T1	126		T2	7961		T13	126
valid_sources[0x16]	1289696	1			T1	114		T2	7985		T13	130
valid_sources[0x17]	1291093	1			T1	119		T2	7847		T13	144
valid_sources[0x18]	2198015	1			T1	118		T2	7850		T13	158
valid_sources[0x19]	1288764	1			T1	115		T2	8025		T13	138
valid_sources[0x1a]	1423056	1			T1	117		T2	7890		T13	137
valid_sources[0x1b]	1598593	1			T1	125		T2	7871		T13	141
valid_sources[0x1c]	1320018	1			T1	115		T2	7939		T13	141
valid_sources[0x1d]	1284230	1			T1	100		T2	7837		T13	117
valid_sources[0x1e]	1361075	1			T1	120		T2	7802		T13	134
valid_sources[0x1f]	1288561	1			T1	98		T2	8172		T13	146
valid_sources[0x20]	2133257	1			T1	114		T2	7955		T13	136
valid_sources[0x21]	3749840	1			T1	120		T2	7942		T13	118
valid_sources[0x22]	1285368	1			T1	126		T2	7881		T13	142
valid_sources[0x23]	3713129	1			T1	124		T2	8012		T13	159
valid_sources[0x24]	2496086	1			T1	104		T2	7979		T13	136
valid_sources[0x25]	1288671	1			T1	110		T2	7773		T13	139
valid_sources[0x26]	3364913	1			T1	107		T2	7750		T13	138
valid_sources[0x27]	1440093	1			T1	108		T2	7788		T13	151
valid_sources[0x28]	1890214	1			T1	117		T2	7999		T13	154
valid_sources[0x29]	2454555	1			T1	125		T2	7763		T13	140
valid_sources[0x2a]	1286266	1			T1	108		T2	7725		T13	147
valid_sources[0x2b]	2158064	1			T1	103		T2	7721		T13	138
valid_sources[0x2c]	1285866	1			T1	103		T2	7957		T13	151
valid_sources[0x2d]	1309519	1			T1	114		T2	7910		T13	140
valid_sources[0x2e]	1329652	1			T1	102		T2	7934		T13	135
valid_sources[0x2f]	2165209	1			T1	127		T2	8064		T13	141
valid_sources[0x30]	1301388	1			T1	100		T2	8188		T13	139
valid_sources[0x31]	1292356	1			T1	112		T2	7790		T13	151
valid_sources[0x32]	3400769	1			T1	106		T2	8075		T13	137
valid_sources[0x33]	2881609	1			T1	128		T2	7666		T13	138
valid_sources[0x34]	1287691	1			T1	107		T2	8011		T13	119
valid_sources[0x35]	1752069	1			T1	118		T2	7899		T13	148
valid_sources[0x36]	3298328	1			T1	97		T2	7884		T13	147
valid_sources[0x37]	1284487	1			T1	106		T2	7806		T13	159
valid_sources[0x38]	4615949	1			T1	123		T2	8308		T13	140
valid_sources[0x39]	1292544	1			T1	110		T2	7813		T13	159
valid_sources[0x3a]	1285633	1			T1	117		T2	7990		T13	128
valid_sources[0x3b]	1284039	1			T1	113		T2	7794		T13	161
valid_sources[0x3c]	1288948	1			T1	103		T2	7826		T13	138
valid_sources[0x3d]	1289665	1			T1	121		T2	7726		T13	154
valid_sources[0x3e]	1298527	1			T1	115		T2	7993		T13	144
valid_sources[0x3f]	1285426	1			T1	107		T2	8020		T13	125
valid_sources[0x40]	4007514	1			T1	117		T2	8078		T3	206275
valid_sources[0x41]	1297705	1			T1	122		T2	8127		T13	137
valid_sources[0x42]	1285922	1			T1	108		T2	7947		T13	157
valid_sources[0x43]	1296843	1			T1	129		T2	7858		T13	158
valid_sources[0x44]	2135839	1			T1	99		T2	7641		T13	121
valid_sources[0x45]	1286373	1			T1	122		T2	7911		T13	119
valid_sources[0x46]	1280712	1			T1	91		T2	7979		T13	141
valid_sources[0x47]	1287283	1			T1	112		T2	7959		T13	141
valid_sources[0x48]	3119046	1			T1	127		T2	8116		T13	138
valid_sources[0x49]	1289690	1			T1	114		T2	7821		T13	126
valid_sources[0x4a]	2194580	1			T1	121		T2	7880		T13	163
valid_sources[0x4b]	1361795	1			T1	102		T2	7812		T13	117
valid_sources[0x4c]	1285123	1			T1	127		T2	7938		T13	153
valid_sources[0x4d]	1340007	1			T1	106		T2	8127		T13	133
valid_sources[0x4e]	1274873	1			T1	96		T2	7789		T13	138
valid_sources[0x4f]	1285179	1			T1	102		T2	7757		T13	163
valid_sources[0x50]	1288161	1			T1	117		T2	7894		T13	134
valid_sources[0x51]	1956931	1			T1	109		T2	7996		T13	156
valid_sources[0x52]	1287829	1			T1	115		T2	8239		T13	130
valid_sources[0x53]	2165321	1			T1	103		T2	7884		T13	152
valid_sources[0x54]	1285478	1			T1	89		T2	7830		T13	143
valid_sources[0x55]	1292850	1			T1	114		T2	8013		T13	129
valid_sources[0x56]	2556740	1			T1	118		T2	7992		T13	136
valid_sources[0x57]	1287725	1			T1	93		T2	8242		T13	134
valid_sources[0x58]	2153232	1			T1	106		T2	7837		T13	137
valid_sources[0x59]	2216118	1			T1	120		T2	8141		T13	118
valid_sources[0x5a]	1288700	1			T1	115		T2	7866		T13	127
valid_sources[0x5b]	4032879	1			T1	125		T2	7935		T13	128
valid_sources[0x5c]	1288752	1			T1	120		T2	8067		T13	140
valid_sources[0x5d]	1284546	1			T1	90		T2	7888		T13	151
valid_sources[0x5e]	3333768	1			T1	114		T2	7728		T13	119
valid_sources[0x5f]	1294150	1			T1	127		T2	8472		T13	155
valid_sources[0x60]	1288418	1			T1	114		T2	7825		T13	145
valid_sources[0x61]	3705670	1			T1	127		T2	7892		T13	149
valid_sources[0x62]	3354216	1			T1	107		T2	8046		T13	148
valid_sources[0x63]	1282341	1			T1	111		T2	7909		T13	150
valid_sources[0x64]	1287938	1			T1	114		T2	8079		T13	151
valid_sources[0x65]	1282804	1			T1	113		T2	8118		T13	149
valid_sources[0x66]	1285112	1			T1	98		T2	8222		T13	127
valid_sources[0x67]	1283604	1			T1	101		T2	8147		T13	143
valid_sources[0x68]	1280290	1			T1	101		T2	7908		T13	145
valid_sources[0x69]	1294140	1			T1	111		T2	8074		T13	129
valid_sources[0x6a]	1539266	1			T1	142		T2	7902		T13	151
valid_sources[0x6b]	1284898	1			T1	101		T2	8049		T13	141
valid_sources[0x6c]	1407093	1			T1	107		T2	8071		T13	119
valid_sources[0x6d]	1278240	1			T1	115		T2	7909		T13	111
valid_sources[0x6e]	1757100	1			T1	124		T2	8347		T13	146
valid_sources[0x6f]	2165100	1			T1	103		T2	8270		T13	128
valid_sources[0x70]	1288981	1			T1	102		T2	7852		T13	130
valid_sources[0x71]	1291897	1			T1	131		T2	7862		T13	142
valid_sources[0x72]	3337856	1			T1	113		T2	7908		T13	129
valid_sources[0x73]	3345943	1			T1	123		T2	7981		T13	162
valid_sources[0x74]	1289496	1			T1	107		T2	8042		T13	134
valid_sources[0x75]	1284352	1			T1	112		T2	8027		T13	130
valid_sources[0x76]	2193499	1			T1	117		T2	7959		T13	142
valid_sources[0x77]	1362860	1			T1	109		T2	7983		T13	140
valid_sources[0x78]	5783383	1			T1	96		T2	7833		T13	145
valid_sources[0x79]	1287489	1			T1	122		T2	7535		T13	120
valid_sources[0x7a]	1299314	1			T1	117		T2	8019		T13	142
valid_sources[0x7b]	1288968	1			T1	121		T2	7837		T13	141
valid_sources[0x7c]	1281101	1			T1	118		T2	7828		T13	143
valid_sources[0x7d]	1400896	1			T1	107		T2	8084		T13	129
valid_sources[0x7e]	1428585	1			T1	123		T2	7871		T13	159
valid_sources[0x7f]	2175133	1			T1	103		T2	8066		T13	141
valid_sources[0x80]	1280224	1			T1	119		T2	7881		T13	134

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85601307

1

T1

53969

T2

419026

T3

421767

values[0x0]

all_enables

biggest_size

59299283

1

T1

35685

T2

254872

T3

253210

values[0x1]

all_enables

biggest_size

50871091

1

T1

30366

T2

214509

T3

212351