Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

250203459

1

T1

154218

T2

115113

T3

117542

full_word

195784387

1

T1

120020

T2

888407

T3

887328

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	445987546	1			T1	274238		T2	203954		T3	206275
auto[TlIntgErrCmd]	90	1			T108	4		T110	5		T111	4
auto[TlIntgErrData]	119	1			T108	11		T110	7		T111	2
auto[TlIntgErrBoth]	91	1			T108	5		T110	8		T111	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235538671

1

T1

147407

T2

110534

T3

111737

auto[1]

210449175

1

T1

126831

T2

934202

T3

945378

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	149934091	1			T1	93438		T2	686314		T3	695608
auto[TlIntgErrNone]	partial	auto[1]	100269093	1			T1	60780		T2	464821		T3	479817
auto[TlIntgErrNone]	full_word	auto[0]	85604448	1			T1	53969		T2	419026		T3	421767
auto[TlIntgErrNone]	full_word	auto[1]	110179914	1			T1	66051		T2	469381		T3	465561
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T110	2		T111	2		T127	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T108	4		T110	2		T111	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T110	1		T154	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T172	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T108	3		T110	1		T111	1
auto[TlIntgErrData]	partial	auto[1]	64	1			T108	7		T110	5		T111	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T108	1		T127	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T110	1		T127	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T108	3		T110	4		T111	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T108	2		T110	4		T127	4
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T154	2		T173	1		T174	2