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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 303973192 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1232 1232 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 303973192 0 0
T1 277029 189819 0 0
T2 216282 139743 0 0
T3 146677 141501 0 0
T13 273609 15296 0 0
T14 204568 712141 0 0
T15 7358 1275 0 0
T16 92881 4576 0 0
T17 432144 140461 0 0
T18 134243 478238 0 0
T19 98165 991 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1232 1232 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 545972046 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1232 1232 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 545972046 0 0
T1 277029 870630 0 0
T2 216282 628564 0 0
T3 146677 141501 0 0
T13 273609 15296 0 0
T14 204568 712141 0 0
T15 7358 1275 0 0
T16 92881 4576 0 0
T17 432144 140461 0 0
T18 134243 478238 0 0
T19 98165 3165 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 277029 277012 0 0
T2 216282 216281 0 0
T3 146677 146677 0 0
T13 273609 273516 0 0
T14 204568 204561 0 0
T15 7358 7263 0 0
T16 92881 92719 0 0
T17 432144 432139 0 0
T18 134243 134235 0 0
T19 98165 98111 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1232 1232 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

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