Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	45321	0	0
entropy_period_rd_A	2147483647	1465	0	0
intr_enable_rd_A	2147483647	2148	0	0
prefix_0_rd_A	2147483647	1477	0	0
prefix_10_rd_A	2147483647	1425	0	0
prefix_1_rd_A	2147483647	1396	0	0
prefix_2_rd_A	2147483647	1452	0	0
prefix_3_rd_A	2147483647	1377	0	0
prefix_4_rd_A	2147483647	1456	0	0
prefix_5_rd_A	2147483647	1407	0	0
prefix_6_rd_A	2147483647	1481	0	0
prefix_7_rd_A	2147483647	1460	0	0
prefix_8_rd_A	2147483647	1458	0	0
prefix_9_rd_A	2147483647	1493	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45321	0	0
T50	438063	42232	0	0
T51	0	97	0	0
T52	0	33	0	0
T108	0	2	0	0
T109	0	128	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	160	0	0
T119	0	179	0	0
T124	0	4	0	0
T128	439071	0	0	0
T129	373536	0	0	0
T130	72780	0	0	0
T131	348685	0	0	0
T132	825489	0	0	0
T133	135170	0	0	0
T134	496041	0	0	0
T135	257640	0	0	0
T136	138135	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1465	0	0
T88	4403	1	0	0
T90	12146	21	0	0
T92	3522	1	0	0
T94	4318	8	0	0
T151	6828	46	0	0
T152	5766	1	0	0
T153	4311	20	0	0
T154	26357	129	0	0
T155	72761	123	0	0
T156	4477	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2148	0	0
T88	4403	21	0	0
T90	12146	57	0	0
T92	3522	17	0	0
T115	1308	15	0	0
T117	1374	32	0	0
T151	6828	28	0	0
T152	5766	23	0	0
T157	1147	20	0	0
T158	2909	2	0	0
T159	1889	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1477	0	0
T88	4403	16	0	0
T90	12146	30	0	0
T92	3522	6	0	0
T102	1979	8	0	0
T151	6828	1	0	0
T152	5766	5	0	0
T153	4311	10	0	0
T154	26357	90	0	0
T155	72761	274	0	0
T158	2909	15	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425	0	0
T88	4403	3	0	0
T90	12146	22	0	0
T92	3522	5	0	0
T102	1979	5	0	0
T151	6828	22	0	0
T152	5766	41	0	0
T153	4311	6	0	0
T154	26357	63	0	0
T155	72761	187	0	0
T158	2909	13	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1396	0	0
T88	4403	19	0	0
T90	12146	30	0	0
T102	1979	2	0	0
T151	6828	20	0	0
T152	5766	24	0	0
T153	4311	9	0	0
T154	26357	85	0	0
T155	72761	203	0	0
T156	4477	7	0	0
T158	2909	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1452	0	0
T88	4403	3	0	0
T90	12146	23	0	0
T92	3522	4	0	0
T102	1979	2	0	0
T151	6828	40	0	0
T152	5766	21	0	0
T153	4311	16	0	0
T154	26357	72	0	0
T155	72761	189	0	0
T156	4477	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1377	0	0
T88	4403	16	0	0
T90	12146	24	0	0
T94	4318	10	0	0
T151	6828	26	0	0
T152	5766	9	0	0
T153	4311	9	0	0
T154	26357	87	0	0
T155	72761	242	0	0
T158	2909	1	0	0
T160	52105	417	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1456	0	0
T88	4403	9	0	0
T90	12146	20	0	0
T94	4318	5	0	0
T102	1979	1	0	0
T151	6828	17	0	0
T152	5766	18	0	0
T153	4311	5	0	0
T154	26357	94	0	0
T155	72761	196	0	0
T156	4477	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1407	0	0
T88	4403	17	0	0
T90	12146	42	0	0
T92	3522	2	0	0
T94	4318	15	0	0
T102	1979	7	0	0
T151	6828	20	0	0
T152	5766	29	0	0
T153	4311	2	0	0
T154	26357	79	0	0
T155	72761	202	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1481	0	0
T88	4403	13	0	0
T90	12146	17	0	0
T92	3522	6	0	0
T94	4318	18	0	0
T102	1979	5	0	0
T151	6828	45	0	0
T152	5766	35	0	0
T153	4311	5	0	0
T154	26357	96	0	0
T155	72761	190	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T88	4403	15	0	0
T90	12146	44	0	0
T92	3522	3	0	0
T102	1979	6	0	0
T109	5840	2	0	0
T151	6828	11	0	0
T152	5766	31	0	0
T153	4311	4	0	0
T154	26357	64	0	0
T158	2909	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T88	4403	21	0	0
T90	12146	27	0	0
T92	3522	3	0	0
T102	1979	4	0	0
T151	6828	15	0	0
T152	5766	9	0	0
T153	4311	13	0	0
T154	26357	87	0	0
T155	72761	220	0	0
T156	4477	12	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1493	0	0
T88	4403	13	0	0
T90	12146	46	0	0
T92	3522	8	0	0
T94	4318	14	0	0
T152	5766	30	0	0
T153	4311	6	0	0
T154	26357	81	0	0
T155	72761	221	0	0
T156	4477	2	0	0
T158	2909	3	0	0