Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
AppKeymgr_cg_(1) 100.00 1 100 1 64 64
AppLc_cg_(1) 100.00 1 100 1 64 64
AppRom_cg_(1) 100.00 1 100 1 64 64




Group Instance : AppKeymgr_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppKeymgr_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppKeymgr_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0



Group Instance : AppLc_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppLc_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppLc_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0



Group Instance : AppRom_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppRom_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppRom_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 1086 1 T14 1 T22 7 T24 1
shake 1140 1 T22 13 T24 4 T25 2
sha3 1107 1 T14 2 T22 5 T24 5


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 563 1 T22 8 T24 3 T40 8
shake 549 1 T22 2 T23 1 T24 4
sha3 605 1 T14 1 T22 2 T24 4


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 531 1 T14 1 T22 4 T24 2
shake 571 1 T14 3 T22 6 T40 9
sha3 591 1 T14 3 T22 3 T25 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%