Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253203586

1

T1

4578

T2

624

T3

288102

full_word

197919749

1

T1

27654

T2

1453

T3

183863

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451123015	1			T1	32232		T2	2077		T3	471965
auto[TlIntgErrCmd]	106	1			T108	5		T109	4		T110	7
auto[TlIntgErrData]	93	1			T108	3		T109	11		T110	7
auto[TlIntgErrBoth]	121	1			T108	2		T109	5		T110	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237830129

1

T1

21615

T2

1081

T3

243047

auto[1]

213293206

1

T1

10617

T2

996

T3

228918

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151438021	1			T1	2524		T2	378		T3	169944
auto[TlIntgErrNone]	partial	auto[1]	101765273	1			T1	2054		T2	246		T3	118158
auto[TlIntgErrNone]	full_word	auto[0]	86391964	1			T1	19091		T2	703		T3	73103
auto[TlIntgErrNone]	full_word	auto[1]	111527757	1			T1	8563		T2	750		T3	110760
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T108	3		T110	3		T160	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T108	1		T109	2		T110	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T110	1		T161	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T108	1		T109	2		T164	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T108	1		T109	4		T110	5
auto[TlIntgErrData]	partial	auto[1]	44	1			T108	1		T109	6		T110	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T108	1		T109	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T165	1		T166	1		T167	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T108	1		T109	3		T110	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T108	1		T109	2		T110	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T110	1		T168	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T164	1		T170	1		T166	1