Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	96.27	93.33	100.00	92.31	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	144764	0	0
entropy_period_rd_A	2147483647	2059	0	0
intr_enable_rd_A	2147483647	3076	0	0
prefix_0_rd_A	2147483647	1880	0	0
prefix_10_rd_A	2147483647	2031	0	0
prefix_1_rd_A	2147483647	1928	0	0
prefix_2_rd_A	2147483647	2047	0	0
prefix_3_rd_A	2147483647	2073	0	0
prefix_4_rd_A	2147483647	1949	0	0
prefix_5_rd_A	2147483647	2008	0	0
prefix_6_rd_A	2147483647	1847	0	0
prefix_7_rd_A	2147483647	2042	0	0
prefix_8_rd_A	2147483647	1891	0	0
prefix_9_rd_A	2147483647	2049	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	144764	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	23465	0	0
T49	0	22099	0	0
T50	0	21718	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T108	0	1	0	0
T109	0	3	0	0
T115	0	73291	0	0
T116	0	1	0	0
T118	0	221	0	0
T119	0	271	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2059	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	45	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	138	0	0
T116	0	14	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	1	0	0
T134	0	22	0	0
T135	0	126	0	0
T136	0	7	0	0
T137	0	24	0	0
T138	0	66	0	0
T139	0	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3076	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	61	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	178	0	0
T116	0	17	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	6	0	0
T134	0	11	0	0
T135	0	195	0	0
T136	0	9	0	0
T140	0	7	0	0
T141	0	17	0	0
T142	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1880	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	7	0	0
T87	8830	0	0	0
T96	0	5	0	0
T103	727748	0	0	0
T109	0	80	0	0
T116	0	3	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T134	0	20	0	0
T135	0	236	0	0
T136	0	3	0	0
T137	0	8	0	0
T138	0	18	0	0
T139	0	24	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2031	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	49	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	77	0	0
T116	0	5	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	5	0	0
T126	0	9	0	0
T134	0	36	0	0
T135	0	226	0	0
T136	0	1	0	0
T137	0	20	0	0
T138	0	51	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1928	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	47	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	74	0	0
T116	0	17	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	7	0	0
T126	0	2	0	0
T134	0	23	0	0
T135	0	209	0	0
T136	0	2	0	0
T137	0	21	0	0
T138	0	41	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2047	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	35	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	93	0	0
T116	0	12	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	7	0	0
T126	0	3	0	0
T134	0	18	0	0
T135	0	196	0	0
T136	0	9	0	0
T137	0	22	0	0
T138	0	42	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2073	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	38	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	93	0	0
T116	0	17	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	6	0	0
T126	0	3	0	0
T134	0	8	0	0
T135	0	223	0	0
T136	0	4	0	0
T137	0	19	0	0
T138	0	45	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1949	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	25	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	61	0	0
T116	0	10	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	1	0	0
T126	0	9	0	0
T134	0	19	0	0
T135	0	223	0	0
T136	0	9	0	0
T137	0	12	0	0
T138	0	33	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	19	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	89	0	0
T116	0	2	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T126	0	8	0	0
T134	0	36	0	0
T135	0	228	0	0
T136	0	6	0	0
T137	0	17	0	0
T138	0	23	0	0
T139	0	19	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	61	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	77	0	0
T116	0	12	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T126	0	4	0	0
T134	0	11	0	0
T135	0	225	0	0
T136	0	9	0	0
T137	0	27	0	0
T138	0	47	0	0
T139	0	12	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2042	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	29	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	88	0	0
T116	0	15	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	13	0	0
T126	0	9	0	0
T134	0	12	0	0
T135	0	224	0	0
T136	0	2	0	0
T137	0	19	0	0
T138	0	31	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1891	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	26	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	83	0	0
T116	0	9	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	5	0	0
T126	0	6	0	0
T134	0	15	0	0
T135	0	263	0	0
T137	0	12	0	0
T138	0	49	0	0
T139	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2049	0	0
T21	179443	0	0	0
T28	195696	0	0	0
T32	267929	33	0	0
T87	8830	0	0	0
T103	727748	0	0	0
T109	0	89	0	0
T116	0	10	0	0
T120	930253	0	0	0
T121	17650	0	0	0
T122	41869	0	0	0
T123	173482	0	0	0
T124	218557	0	0	0
T125	0	2	0	0
T126	0	6	0	0
T134	0	28	0	0
T135	0	220	0	0
T136	0	5	0	0
T137	0	8	0	0
T138	0	53	0	0