Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253686472	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198586450

1

T1

524358

T2

359259

T3

158295

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238800857	1			T1	661471		T2	467063		T3	71450
values[0x0]	102594700	1			T1	285379		T2	215081		T3	57791
values[0x1]	110877365	1			T1	308383		T2	233115		T3	59085

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197818017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254454905

1

T1

684255

T2

480885

T3

165249

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2979468	1			T1	4654		T3	756		T13	2679
valid_sources[0x01]	2200420	1			T1	4835		T3	536		T13	2544
valid_sources[0x02]	1341894	1			T1	4861		T3	787		T13	2585
valid_sources[0x03]	1339709	1			T1	5168		T3	639		T13	2762
valid_sources[0x04]	1337767	1			T1	4416		T3	695		T13	2537
valid_sources[0x05]	1335374	1			T1	5305		T3	634		T13	2692
valid_sources[0x06]	1336788	1			T1	4987		T3	710		T13	2758
valid_sources[0x07]	1341770	1			T1	4778		T3	835		T13	2760
valid_sources[0x08]	1342827	1			T1	4564		T3	733		T13	2817
valid_sources[0x09]	1465262	1			T1	4571		T3	860		T13	2432
valid_sources[0x0a]	1471569	1			T1	5164		T3	789		T13	2498
valid_sources[0x0b]	1360410	1			T1	4495		T3	672		T13	2620
valid_sources[0x0c]	2011646	1			T1	4893		T3	785		T13	2559
valid_sources[0x0d]	1421795	1			T1	4503		T3	619		T13	2722
valid_sources[0x0e]	1341896	1			T1	4954		T3	779		T13	2618
valid_sources[0x0f]	1342953	1			T1	4669		T3	670		T13	2569
valid_sources[0x10]	1338476	1			T1	4785		T3	811		T13	2540
valid_sources[0x11]	1339060	1			T1	4887		T3	799		T13	2675
valid_sources[0x12]	2243184	1			T1	4841		T3	811		T13	2670
valid_sources[0x13]	3471992	1			T1	5235		T3	633		T13	2725
valid_sources[0x14]	1660882	1			T1	4931		T3	654		T13	2608
valid_sources[0x15]	1341666	1			T1	4871		T3	568		T13	2471
valid_sources[0x16]	1338991	1			T1	4880		T3	758		T13	2668
valid_sources[0x17]	2065468	1			T1	4475		T3	715		T13	2741
valid_sources[0x18]	1337603	1			T1	4452		T3	736		T13	2729
valid_sources[0x19]	2214200	1			T1	4631		T3	844		T13	2791
valid_sources[0x1a]	1343331	1			T1	5638		T3	683		T13	2455
valid_sources[0x1b]	1339593	1			T1	4215		T3	857		T13	2593
valid_sources[0x1c]	1340100	1			T1	4929		T3	771		T13	2708
valid_sources[0x1d]	1342667	1			T1	4550		T3	730		T13	2462
valid_sources[0x1e]	1338741	1			T1	4826		T3	798		T13	2483
valid_sources[0x1f]	1340265	1			T1	4896		T3	812		T13	2479
valid_sources[0x20]	3765506	1			T1	4413		T3	754		T13	2602
valid_sources[0x21]	1335290	1			T1	5295		T3	825		T13	2377
valid_sources[0x22]	1883417	1			T1	5429		T3	709		T13	2782
valid_sources[0x23]	1336726	1			T1	4670		T3	667		T13	2503
valid_sources[0x24]	1340014	1			T1	5198		T3	694		T13	2332
valid_sources[0x25]	1336855	1			T1	4233		T3	771		T13	2601
valid_sources[0x26]	1341246	1			T1	5158		T3	737		T13	2647
valid_sources[0x27]	1334007	1			T1	5065		T3	686		T13	2553
valid_sources[0x28]	1338296	1			T1	4878		T3	784		T13	2543
valid_sources[0x29]	1370118	1			T1	4846		T3	599		T13	2738
valid_sources[0x2a]	1822617	1			T1	4936		T3	678		T13	2867
valid_sources[0x2b]	1330520	1			T1	4572		T3	775		T13	2677
valid_sources[0x2c]	3744398	1			T1	4685		T3	697		T13	2540
valid_sources[0x2d]	1342017	1			T1	4484		T3	798		T13	2848
valid_sources[0x2e]	1629737	1			T1	5519		T3	761		T13	2595
valid_sources[0x2f]	1345272	1			T1	4788		T3	713		T13	2623
valid_sources[0x30]	1341782	1			T1	4766		T3	629		T13	2462
valid_sources[0x31]	1799777	1			T1	4800		T3	695		T13	2762
valid_sources[0x32]	1342111	1			T1	5408		T3	712		T13	2703
valid_sources[0x33]	1345661	1			T1	5164		T3	838		T13	2550
valid_sources[0x34]	1336147	1			T1	4947		T3	877		T13	2426
valid_sources[0x35]	1336265	1			T1	4643		T3	778		T13	2416
valid_sources[0x36]	1336341	1			T1	4869		T3	803		T13	2597
valid_sources[0x37]	3387440	1			T1	4717		T3	694		T13	2550
valid_sources[0x38]	1333705	1			T1	4987		T3	750		T13	2790
valid_sources[0x39]	1345750	1			T1	4896		T3	840		T13	2533
valid_sources[0x3a]	1334654	1			T1	5043		T3	743		T13	2815
valid_sources[0x3b]	1342857	1			T1	5160		T3	639		T13	2737
valid_sources[0x3c]	6667717	1			T1	5081		T3	723		T13	2652
valid_sources[0x3d]	1339979	1			T1	4984		T3	694		T13	2904
valid_sources[0x3e]	1342065	1			T1	4567		T3	684		T13	2293
valid_sources[0x3f]	1340124	1			T1	5212		T3	800		T13	2650
valid_sources[0x40]	1341918	1			T1	4906		T3	616		T13	2603
valid_sources[0x41]	1419513	1			T1	5021		T3	716		T13	2598
valid_sources[0x42]	1338845	1			T1	4574		T3	638		T13	2814
valid_sources[0x43]	3430559	1			T1	4972		T3	726		T13	2433
valid_sources[0x44]	1335205	1			T1	5034		T3	790		T13	2473
valid_sources[0x45]	2166046	1			T1	5266		T3	741		T13	2634
valid_sources[0x46]	1337458	1			T1	4926		T3	644		T13	2638
valid_sources[0x47]	1486141	1			T1	5061		T3	769		T13	2614
valid_sources[0x48]	1347838	1			T1	5121		T3	778		T13	2571
valid_sources[0x49]	1335333	1			T1	5090		T3	829		T13	2561
valid_sources[0x4a]	1336961	1			T1	5269		T3	801		T13	2423
valid_sources[0x4b]	1335956	1			T1	4999		T3	781		T13	2448
valid_sources[0x4c]	1338447	1			T1	4929		T3	778		T13	2739
valid_sources[0x4d]	1337419	1			T1	5029		T3	704		T13	2748
valid_sources[0x4e]	1338296	1			T1	5099		T3	793		T13	2595
valid_sources[0x4f]	1385803	1			T1	4670		T3	729		T13	2762
valid_sources[0x50]	2211471	1			T1	4825		T3	736		T13	2663
valid_sources[0x51]	2611701	1			T1	5017		T3	691		T13	2462
valid_sources[0x52]	3423688	1			T1	5119		T3	653		T13	2616
valid_sources[0x53]	1600637	1			T1	4593		T3	676		T13	2629
valid_sources[0x54]	1351565	1			T1	4819		T3	741		T13	2384
valid_sources[0x55]	1440635	1			T1	5257		T3	690		T13	2827
valid_sources[0x56]	1338215	1			T1	4776		T3	664		T13	2947
valid_sources[0x57]	1339002	1			T1	4700		T3	664		T13	2733
valid_sources[0x58]	1356195	1			T1	4675		T3	793		T13	2590
valid_sources[0x59]	1432523	1			T1	5264		T3	658		T13	2642
valid_sources[0x5a]	2340687	1			T1	4747		T2	915259		T3	686
valid_sources[0x5b]	1337784	1			T1	4754		T3	771		T13	2585
valid_sources[0x5c]	4198904	1			T1	5148		T3	877		T13	2307
valid_sources[0x5d]	1339221	1			T1	4424		T3	811		T13	2567
valid_sources[0x5e]	1812970	1			T1	5005		T3	830		T13	2509
valid_sources[0x5f]	1364977	1			T1	4833		T3	744		T13	2747
valid_sources[0x60]	1334310	1			T1	4864		T3	775		T13	2797
valid_sources[0x61]	1341036	1			T1	4913		T3	781		T13	2856
valid_sources[0x62]	1346700	1			T1	5034		T3	756		T13	2819
valid_sources[0x63]	1339964	1			T1	4391		T3	618		T13	2603
valid_sources[0x64]	1338048	1			T1	4971		T3	696		T13	2609
valid_sources[0x65]	1339092	1			T1	5012		T3	852		T13	2786
valid_sources[0x66]	1334369	1			T1	4758		T3	763		T13	2798
valid_sources[0x67]	1487286	1			T1	4769		T3	678		T13	2625
valid_sources[0x68]	1339310	1			T1	5189		T3	607		T13	2748
valid_sources[0x69]	1507842	1			T1	4831		T3	701		T13	2678
valid_sources[0x6a]	1339096	1			T1	4459		T3	746		T13	2795
valid_sources[0x6b]	3014661	1			T1	5165		T3	766		T13	2696
valid_sources[0x6c]	2250432	1			T1	4685		T3	671		T13	2697
valid_sources[0x6d]	3400952	1			T1	4248		T3	816		T13	2526
valid_sources[0x6e]	4060102	1			T1	4807		T3	739		T13	2688
valid_sources[0x6f]	1347487	1			T1	4981		T3	774		T13	2708
valid_sources[0x70]	3875353	1			T1	5042		T3	659		T13	2666
valid_sources[0x71]	1379318	1			T1	5298		T3	779		T13	2709
valid_sources[0x72]	3405559	1			T1	5133		T3	654		T13	2552
valid_sources[0x73]	1330413	1			T1	4843		T3	689		T13	2383
valid_sources[0x74]	1338615	1			T1	4930		T3	755		T13	2727
valid_sources[0x75]	2190554	1			T1	5120		T3	742		T13	2749
valid_sources[0x76]	1348177	1			T1	5091		T3	695		T13	2712
valid_sources[0x77]	1394364	1			T1	5421		T3	773		T13	2529
valid_sources[0x78]	1342263	1			T1	5300		T3	823		T13	2674
valid_sources[0x79]	1340647	1			T1	4606		T3	753		T13	2615
valid_sources[0x7a]	1998415	1			T1	4801		T3	668		T13	2671
valid_sources[0x7b]	2569786	1			T1	4646		T3	764		T13	2525
valid_sources[0x7c]	1337106	1			T1	4983		T3	747		T13	2804
valid_sources[0x7d]	1342118	1			T1	4937		T3	706		T13	2638
valid_sources[0x7e]	1336957	1			T1	4658		T3	710		T13	2545
valid_sources[0x7f]	1334594	1			T1	4755		T3	659		T13	2759
valid_sources[0x80]	1458284	1			T1	4876		T3	693		T13	2615

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86665026

1

T1

219805

T2

133843

T3

51135

values[0x0]

all_enables

biggest_size

60243622

1

T1

164515

T2

122256

T3

53731

values[0x1]

all_enables

biggest_size

51677802

1

T1

140038

T2

103160

T3

53429