SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 308297515 | 1 | T1 | 890445 | T2 | 671393 | T3 | 41209 | ||||
auto[1] | 143992299 | 1 | T1 | 364788 | T2 | 243866 | T3 | 147117 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 452289584 | 1 | T1 | 125523 | T2 | 915259 | T3 | 188326 | ||||
values[1] | 31 | 1 | T126 | 2 | T183 | 2 | T153 | 2 | ||||
values[2] | 5 | 1 | T55 | 1 | T183 | 2 | T153 | 1 | ||||
values[3] | 113 | 1 | T55 | 6 | T126 | 6 | T127 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 452289588 | 1 | T1 | 125523 | T2 | 915259 | T3 | 188326 | ||||
values[1] | 21 | 1 | T55 | 2 | T126 | 1 | T127 | 1 | ||||
values[2] | 5 | 1 | T126 | 1 | T184 | 1 | T185 | 1 | ||||
values[3] | 107 | 1 | T55 | 8 | T126 | 6 | T127 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 452289464 | 1 | T1 | 125523 | T2 | 915259 | T3 | 188326 | ||||
auto[TlIntgErrCmd] | 124 | 1 | T55 | 5 | T126 | 6 | T127 | 5 | ||||
auto[TlIntgErrData] | 120 | 1 | T55 | 10 | T126 | 9 | T127 | 9 | ||||
auto[TlIntgErrBoth] | 106 | 1 | T55 | 5 | T126 | 5 | T127 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |