Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253702281

1

T1

730875

T2

556000

T3

30031

full_word

198587533

1

T1

524358

T2

359259

T3

158295

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452289464	1			T1	125523		T2	915259		T3	188326
auto[TlIntgErrCmd]	124	1			T55	5		T126	6		T127	5
auto[TlIntgErrData]	120	1			T55	10		T126	9		T127	9
auto[TlIntgErrBoth]	106	1			T55	5		T126	5		T127	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238804117

1

T1

661471

T2

467063

T3

71450

auto[1]

213485697

1

T1

593762

T2

448196

T3

116876

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	152138658	1			T1	441666		T2	333220		T3	20315
auto[TlIntgErrNone]	partial	auto[1]	101563311	1			T1	289209		T2	222780		T3	9716
auto[TlIntgErrNone]	full_word	auto[0]	86665297	1			T1	219805		T2	133843		T3	51135
auto[TlIntgErrNone]	full_word	auto[1]	111922198	1			T1	304553		T2	225416		T3	107160
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T55	1		T127	2		T183	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T55	2		T126	5		T127	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T55	1		T126	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T55	1		T183	2		T153	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T55	3		T126	5		T127	5
auto[TlIntgErrData]	partial	auto[1]	50	1			T55	7		T126	2		T127	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T126	2		T127	1		T153	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T183	2		T154	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T55	3		T126	1		T127	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T55	1		T126	4		T127	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T186	1		T187	1		T185	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T55	1		T127	1		T154	1