Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3550	0	0
entropy_period_rd_A	2147483647	1602	0	0
intr_enable_rd_A	2147483647	2136	0	0
prefix_0_rd_A	2147483647	1507	0	0
prefix_10_rd_A	2147483647	1605	0	0
prefix_1_rd_A	2147483647	1603	0	0
prefix_2_rd_A	2147483647	1520	0	0
prefix_3_rd_A	2147483647	1486	0	0
prefix_4_rd_A	2147483647	1547	0	0
prefix_5_rd_A	2147483647	1441	0	0
prefix_6_rd_A	2147483647	1466	0	0
prefix_7_rd_A	2147483647	1471	0	0
prefix_8_rd_A	2147483647	1443	0	0
prefix_9_rd_A	2147483647	1499	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3550	0	0
T54	3445	138	0	0
T55	8626	1	0	0
T56	4252	265	0	0
T112	3820	2	0	0
T125	4022	1	0	0
T126	9626	1	0	0
T128	2963	130	0	0
T130	3923	267	0	0
T141	2360	92	0	0
T142	2854	9	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602	0	0
T125	4022	12	0	0
T140	4250	20	0	0
T153	22426	124	0	0
T154	21559	41	0	0
T155	10150	15	0	0
T156	11209	23	0	0
T157	11292	56	0	0
T158	4332	10	0	0
T159	26473	212	0	0
T160	1714	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T125	4022	2	0	0
T140	4250	10	0	0
T153	22426	148	0	0
T154	21559	91	0	0
T155	10150	1	0	0
T156	11209	58	0	0
T161	1942	18	0	0
T162	995	3	0	0
T163	1376	3	0	0
T164	1103	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1507	0	0
T125	4022	11	0	0
T140	4250	14	0	0
T153	22426	102	0	0
T154	21559	53	0	0
T155	10150	30	0	0
T156	11209	13	0	0
T157	11292	39	0	0
T158	4332	15	0	0
T159	26473	218	0	0
T165	12752	55	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1605	0	0
T125	4022	10	0	0
T136	9706	1	0	0
T140	4250	13	0	0
T153	22426	103	0	0
T154	21559	66	0	0
T155	10150	8	0	0
T156	11209	49	0	0
T157	11292	74	0	0
T158	4332	10	0	0
T159	26473	220	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T125	4022	14	0	0
T140	4250	7	0	0
T153	22426	74	0	0
T154	21559	58	0	0
T155	10150	32	0	0
T156	11209	46	0	0
T157	11292	63	0	0
T158	4332	11	0	0
T159	26473	209	0	0
T160	1714	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1520	0	0
T125	4022	15	0	0
T135	14863	4	0	0
T140	4250	7	0	0
T153	22426	108	0	0
T154	21559	31	0	0
T155	10150	32	0	0
T156	11209	52	0	0
T157	11292	23	0	0
T158	4332	10	0	0
T159	26473	159	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1486	0	0
T125	4022	5	0	0
T135	14863	7	0	0
T140	4250	12	0	0
T153	22426	92	0	0
T154	21559	43	0	0
T155	10150	20	0	0
T156	11209	56	0	0
T157	11292	10	0	0
T158	4332	13	0	0
T159	26473	229	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T125	4022	12	0	0
T140	4250	3	0	0
T153	22426	75	0	0
T154	21559	53	0	0
T155	10150	14	0	0
T156	11209	65	0	0
T157	11292	44	0	0
T158	4332	6	0	0
T159	26473	196	0	0
T160	1714	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1441	0	0
T125	4022	7	0	0
T140	4250	10	0	0
T153	22426	79	0	0
T154	21559	35	0	0
T155	10150	25	0	0
T156	11209	24	0	0
T157	11292	19	0	0
T158	4332	7	0	0
T159	26473	187	0	0
T165	12752	40	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1466	0	0
T125	4022	9	0	0
T140	4250	16	0	0
T153	22426	85	0	0
T154	21559	34	0	0
T155	10150	20	0	0
T156	11209	54	0	0
T157	11292	63	0	0
T158	4332	9	0	0
T159	26473	233	0	0
T160	1714	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1471	0	0
T125	4022	13	0	0
T140	4250	9	0	0
T153	22426	92	0	0
T154	21559	44	0	0
T155	10150	55	0	0
T156	11209	17	0	0
T157	11292	41	0	0
T158	4332	9	0	0
T159	26473	224	0	0
T165	12752	43	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1443	0	0
T125	4022	11	0	0
T140	4250	10	0	0
T153	22426	67	0	0
T154	21559	34	0	0
T155	10150	15	0	0
T156	11209	38	0	0
T157	11292	49	0	0
T158	4332	13	0	0
T159	26473	199	0	0
T160	1714	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1499	0	0
T125	4022	5	0	0
T140	4250	13	0	0
T153	22426	79	0	0
T154	21559	29	0	0
T155	10150	16	0	0
T156	11209	63	0	0
T157	11292	54	0	0
T158	4332	7	0	0
T159	26473	216	0	0
T160	1714	3	0	0