Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

252553013

1

T1

2680

T2

26164

T3

407366

full_word

197549118

1

T1

5041

T2

137844

T3

261523

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450101811	1			T1	7721		T2	164008		T3	668889
auto[TlIntgErrCmd]	102	1			T101	4		T102	3		T103	6
auto[TlIntgErrData]	126	1			T101	4		T102	2		T103	9
auto[TlIntgErrBoth]	92	1			T101	2		T102	5		T103	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237475156

1

T1

5396

T2

55293

T3

342715

auto[1]

212626975

1

T1

2325

T2

108715

T3

326174

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151385692	1			T1	1531		T2	24536		T3	242319
auto[TlIntgErrNone]	partial	auto[1]	101167039	1			T1	1149		T2	1628		T3	165047
auto[TlIntgErrNone]	full_word	auto[0]	86089321	1			T1	3865		T2	30757		T3	100396
auto[TlIntgErrNone]	full_word	auto[1]	111459759	1			T1	1176		T2	107087		T3	161127
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T101	2		T102	1		T103	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T101	2		T102	2		T103	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T103	1		T157	1		T159	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T156	1		T155	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T101	2		T102	1		T103	6
auto[TlIntgErrData]	partial	auto[1]	55	1			T101	1		T102	1		T103	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T101	1		T157	1		T160	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T156	1		T155	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T102	1		T103	3		T156	4
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T101	2		T102	4		T103	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T156	2		T162	2		T163	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T155	1		T157	2		T159	2