Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	51382	0	0
entropy_period_rd_A	2147483647	1791	0	0
intr_enable_rd_A	2147483647	2428	0	0
prefix_0_rd_A	2147483647	1980	0	0
prefix_10_rd_A	2147483647	1865	0	0
prefix_1_rd_A	2147483647	1868	0	0
prefix_2_rd_A	2147483647	1905	0	0
prefix_3_rd_A	2147483647	2088	0	0
prefix_4_rd_A	2147483647	1934	0	0
prefix_5_rd_A	2147483647	1837	0	0
prefix_6_rd_A	2147483647	1973	0	0
prefix_7_rd_A	2147483647	1990	0	0
prefix_8_rd_A	2147483647	1782	0	0
prefix_9_rd_A	2147483647	1721	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51382	0	0
T7	5879	0	0	0
T32	523020	47955	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T52	0	135	0	0
T53	0	140	0	0
T100	0	253	0	0
T104	0	218	0	0
T108	0	156	0	0
T112	0	3	0	0
T113	0	7	0	0
T114	0	2	0	0
T115	0	15	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T7	5879	0	0	0
T32	523020	98	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	39	0	0
T90	0	17	0	0
T94	0	50	0	0
T113	0	8	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	97	0	0
T132	0	18	0	0
T133	0	48	0	0
T134	0	46	0	0
T135	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T7	5879	0	0	0
T32	523020	113	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	77	0	0
T106	0	12	0	0
T113	0	30	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	221	0	0
T132	0	26	0	0
T133	0	46	0	0
T136	0	9	0	0
T137	0	6	0	0
T138	0	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1980	0	0
T7	5879	0	0	0
T32	523020	137	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	37	0	0
T90	0	21	0	0
T94	0	48	0	0
T113	0	12	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	236	0	0
T132	0	5	0	0
T133	0	86	0	0
T134	0	54	0	0
T137	0	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1865	0	0
T7	5879	0	0	0
T32	523020	110	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	20	0	0
T90	0	23	0	0
T94	0	46	0	0
T113	0	12	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	237	0	0
T133	0	66	0	0
T134	0	9	0	0
T135	0	6	0	0
T137	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T7	5879	0	0	0
T32	523020	135	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	27	0	0
T90	0	23	0	0
T110	0	2	0	0
T113	0	4	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	205	0	0
T132	0	7	0	0
T133	0	25	0	0
T134	0	13	0	0
T137	0	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T7	5879	0	0	0
T32	523020	101	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	15	0	0
T90	0	21	0	0
T94	0	36	0	0
T113	0	18	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	227	0	0
T132	0	25	0	0
T133	0	59	0	0
T134	0	47	0	0
T137	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T7	5879	0	0	0
T32	523020	127	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	26	0	0
T90	0	15	0	0
T94	0	66	0	0
T113	0	11	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	251	0	0
T132	0	9	0	0
T133	0	60	0	0
T134	0	47	0	0
T137	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1934	0	0
T7	5879	0	0	0
T32	523020	114	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	12	0	0
T90	0	25	0	0
T94	0	53	0	0
T113	0	6	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	192	0	0
T132	0	37	0	0
T133	0	45	0	0
T134	0	17	0	0
T137	0	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T7	5879	0	0	0
T32	523020	117	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	24	0	0
T90	0	32	0	0
T94	0	40	0	0
T113	0	8	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	242	0	0
T132	0	21	0	0
T133	0	45	0	0
T134	0	22	0	0
T137	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1973	0	0
T7	5879	0	0	0
T32	523020	81	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	29	0	0
T90	0	22	0	0
T94	0	60	0	0
T113	0	11	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	221	0	0
T132	0	9	0	0
T133	0	83	0	0
T134	0	34	0	0
T137	0	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T7	5879	0	0	0
T32	523020	136	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	34	0	0
T90	0	14	0	0
T94	0	41	0	0
T113	0	4	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	260	0	0
T132	0	9	0	0
T133	0	31	0	0
T134	0	30	0	0
T137	0	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T7	5879	0	0	0
T32	523020	76	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	29	0	0
T90	0	11	0	0
T94	0	42	0	0
T110	0	4	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	191	0	0
T132	0	16	0	0
T133	0	43	0	0
T134	0	27	0	0
T137	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1721	0	0
T7	5879	0	0	0
T32	523020	121	0	0
T36	100365	0	0	0
T49	270700	0	0	0
T86	0	20	0	0
T90	0	12	0	0
T94	0	52	0	0
T113	0	16	0	0
T116	22711	0	0	0
T117	3330	0	0	0
T118	504241	0	0	0
T119	275649	0	0	0
T120	359177	0	0	0
T121	2096	0	0	0
T131	0	183	0	0
T132	0	17	0	0
T133	0	22	0	0
T134	0	20	0	0
T137	0	6	0	0