Unified Coverage Report :: Group :: kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg

Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
AppKeymgr_cg_(1)	100.00	1	100	1	64	64
AppLc_cg_(1)	100.00	1	100	1	64	64
AppRom_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : AppKeymgr_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppKeymgr_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppKeymgr_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

---

Group Instance : AppLc_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppLc_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppLc_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

---

Group Instance : AppRom_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance AppRom_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance AppRom_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sw_configured_hash_mode	3	0	3	100.00	100	1	1	0

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	1048	1			T3	8		T21	6		T22	2
shake	1031	1			T3	5		T21	13		T22	1
sha3	1080	1			T3	13		T21	12		T22	2

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	562	1			T3	5		T21	4		T25	2
shake	582	1			T3	3		T21	6		T22	2
sha3	600	1			T3	2		T21	4		T22	1

Summary for Variable sw_configured_hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for sw_configured_hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	537	1			T3	2		T21	6		T22	4
shake	510	1			T3	2		T21	6		T26	1
sha3	554	1			T3	2		T21	4		T26	1