Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253442662

1

T1

175

T2

4252

T3

154175

full_word

196630886

1

T1

726

T2

27103

T3

158654

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450073258	1			T1	901		T2	31355		T3	312829
auto[TlIntgErrCmd]	100	1			T112	5		T113	9		T114	10
auto[TlIntgErrData]	80	1			T112	6		T113	2		T114	8
auto[TlIntgErrBoth]	110	1			T112	9		T113	9		T114	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237099869

1

T1

164

T2

21397

T3

182437

auto[1]

212973679

1

T1

737

T2

9958

T3

130392

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151389778	1			T1	134		T2	2366		T3	92415
auto[TlIntgErrNone]	partial	auto[1]	102052618	1			T1	41		T2	1886		T3	61760
auto[TlIntgErrNone]	full_word	auto[0]	85709969	1			T1	30		T2	19031		T3	90022
auto[TlIntgErrNone]	full_word	auto[1]	110920893	1			T1	696		T2	8072		T3	68632
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T112	2		T113	2		T114	5
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T112	2		T113	7		T114	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T112	1		T114	1		T176	2
auto[TlIntgErrData]	partial	auto[0]	34	1			T112	3		T113	1		T114	6
auto[TlIntgErrData]	partial	auto[1]	39	1			T112	3		T113	1		T114	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T176	1		T175	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T178	1		T179	1		T180	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T112	3		T113	5		T114	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T112	6		T113	2		T114	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T176	1		T174	1		T181	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T113	2		T176	1		T175	2