Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	279238	0	0
entropy_period_rd_A	2147483647	1015	0	0
intr_enable_rd_A	2147483647	1261	0	0
prefix_0_rd_A	2147483647	870	0	0
prefix_10_rd_A	2147483647	824	0	0
prefix_1_rd_A	2147483647	866	0	0
prefix_2_rd_A	2147483647	851	0	0
prefix_3_rd_A	2147483647	891	0	0
prefix_4_rd_A	2147483647	758	0	0
prefix_5_rd_A	2147483647	810	0	0
prefix_6_rd_A	2147483647	783	0	0
prefix_7_rd_A	2147483647	802	0	0
prefix_8_rd_A	2147483647	830	0	0
prefix_9_rd_A	2147483647	767	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	279238	0	0
T30	139304	140259	0	0
T46	0	44611	0	0
T47	0	35819	0	0
T112	0	1	0	0
T113	0	2	0	0
T118	0	54911	0	0
T119	0	149	0	0
T120	0	103	0	0
T121	0	111	0	0
T122	0	247	0	0
T123	23425	0	0	0
T124	62808	0	0	0
T125	244890	0	0	0
T126	686051	0	0	0
T127	176717	0	0	0
T128	130691	0	0	0
T129	24804	0	0	0
T130	323340	0	0	0
T131	988728	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1015	0	0
T100	4466	12	0	0
T102	6012	17	0	0
T105	2274	2	0	0
T145	2769	9	0	0
T146	10648	15	0	0
T147	12205	62	0	0
T148	11468	67	0	0
T149	3947	15	0	0
T150	5637	29	0	0
T151	5905	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261	0	0
T105	2274	3	0	0
T109	1997	3	0	0
T117	1444	23	0	0
T145	2769	8	0	0
T146	10648	36	0	0
T147	12205	101	0	0
T148	11468	40	0	0
T149	3947	4	0	0
T150	5637	18	0	0
T152	1447	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	870	0	0
T100	4466	10	0	0
T105	2274	3	0	0
T109	1997	3	0	0
T145	2769	6	0	0
T146	10648	51	0	0
T147	12205	44	0	0
T148	11468	62	0	0
T149	3947	18	0	0
T150	5637	16	0	0
T153	6491	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	824	0	0
T105	2274	1	0	0
T119	7016	1	0	0
T145	2769	9	0	0
T146	10648	69	0	0
T147	12205	54	0	0
T148	11468	20	0	0
T149	3947	8	0	0
T150	5637	7	0	0
T153	6491	21	0	0
T154	14582	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	866	0	0
T100	4466	7	0	0
T102	6012	14	0	0
T105	2274	8	0	0
T145	2769	6	0	0
T146	10648	74	0	0
T147	12205	56	0	0
T148	11468	35	0	0
T149	3947	4	0	0
T150	5637	7	0	0
T153	6491	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	851	0	0
T100	4466	16	0	0
T105	2274	1	0	0
T109	1997	6	0	0
T145	2769	1	0	0
T146	10648	39	0	0
T147	12205	37	0	0
T148	11468	38	0	0
T149	3947	15	0	0
T150	5637	5	0	0
T153	6491	11	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	891	0	0
T100	4466	10	0	0
T102	6012	11	0	0
T145	2769	8	0	0
T146	10648	55	0	0
T147	12205	55	0	0
T148	11468	64	0	0
T149	3947	18	0	0
T150	5637	7	0	0
T151	5905	9	0	0
T153	6491	31	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	758	0	0
T105	2274	7	0	0
T109	1997	5	0	0
T145	2769	7	0	0
T146	10648	22	0	0
T147	12205	27	0	0
T148	11468	33	0	0
T149	3947	10	0	0
T150	5637	9	0	0
T153	6491	25	0	0
T154	14582	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	810	0	0
T100	4466	3	0	0
T102	6012	23	0	0
T105	2274	2	0	0
T109	1997	7	0	0
T145	2769	5	0	0
T146	10648	34	0	0
T147	12205	36	0	0
T148	11468	57	0	0
T149	3947	9	0	0
T153	6491	22	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	783	0	0
T100	4466	17	0	0
T102	6012	6	0	0
T145	2769	9	0	0
T146	10648	14	0	0
T147	12205	45	0	0
T148	11468	53	0	0
T149	3947	11	0	0
T150	5637	22	0	0
T151	5905	14	0	0
T153	6491	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	802	0	0
T100	4466	16	0	0
T102	6012	14	0	0
T109	1997	6	0	0
T145	2769	6	0	0
T146	10648	54	0	0
T147	12205	41	0	0
T148	11468	62	0	0
T149	3947	5	0	0
T150	5637	4	0	0
T153	6491	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	830	0	0
T100	4466	11	0	0
T102	6012	10	0	0
T105	2274	5	0	0
T145	2769	5	0	0
T146	10648	67	0	0
T147	12205	38	0	0
T148	11468	24	0	0
T149	3947	16	0	0
T150	5637	14	0	0
T153	6491	15	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	767	0	0
T105	2274	3	0	0
T109	1997	3	0	0
T145	2769	2	0	0
T146	10648	53	0	0
T147	12205	42	0	0
T148	11468	31	0	0
T149	3947	11	0	0
T150	5637	15	0	0
T153	6491	3	0	0
T154	14582	1	0	0