Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253263480

1

T1

9512

T2

398294

T3

282546

full_word

198156310

1

T1

16788

T2

261598

T3

183786

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451419500	1			T1	26300		T2	659892		T3	466332
auto[TlIntgErrCmd]	93	1			T115	4		T116	3		T117	10
auto[TlIntgErrData]	101	1			T115	5		T116	6		T117	8
auto[TlIntgErrBoth]	96	1			T115	1		T116	1		T117	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238206381

1

T1

18450

T2

338207

T3

240223

auto[1]

213213409

1

T1

7850

T2

321685

T3

226109

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151801174	1			T1	6142		T2	239184		T3	167967
auto[TlIntgErrNone]	partial	auto[1]	101462044	1			T1	3370		T2	159110		T3	114579
auto[TlIntgErrNone]	full_word	auto[0]	86405069	1			T1	12308		T2	99023		T3	72256
auto[TlIntgErrNone]	full_word	auto[1]	111751213	1			T1	4480		T2	162575		T3	111530
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T115	1		T116	1		T117	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T115	3		T116	1		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T184	1		T187	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T117	2		T184	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T115	1		T116	2		T117	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T115	3		T116	2		T117	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T116	1		T117	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T115	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T115	1		T182	3		T183	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T116	1		T117	2		T182	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T183	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T186	1		-	-		-	-