Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	57070	0	0
entropy_period_rd_A	2147483647	1632	0	0
intr_enable_rd_A	2147483647	2227	0	0
prefix_0_rd_A	2147483647	1249	0	0
prefix_10_rd_A	2147483647	1288	0	0
prefix_1_rd_A	2147483647	1231	0	0
prefix_2_rd_A	2147483647	1384	0	0
prefix_3_rd_A	2147483647	1342	0	0
prefix_4_rd_A	2147483647	1349	0	0
prefix_5_rd_A	2147483647	1328	0	0
prefix_6_rd_A	2147483647	1340	0	0
prefix_7_rd_A	2147483647	1290	0	0
prefix_8_rd_A	2147483647	1372	0	0
prefix_9_rd_A	2147483647	1424	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	57070	0	0
T52	367812	37593	0	0
T53	0	16033	0	0
T54	0	291	0	0
T115	0	2	0	0
T123	0	253	0	0
T126	0	7	0	0
T132	0	1	0	0
T133	0	7	0	0
T134	0	67	0	0
T135	0	6	0	0
T136	134431	0	0	0
T137	699116	0	0	0
T138	39048	0	0	0
T139	853895	0	0	0
T140	4172	0	0	0
T141	6464	0	0	0
T142	663813	0	0	0
T143	461252	0	0	0
T144	16527	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1632	0	0
T103	6716	57	0	0
T104	2131	3	0	0
T116	12741	83	0	0
T117	24394	121	0	0
T152	2790	13	0	0
T153	1711	4	0	0
T154	10557	30	0	0
T155	11709	105	0	0
T156	11646	25	0	0
T157	8017	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T103	6716	19	0	0
T104	2131	1	0	0
T116	12741	58	0	0
T117	24394	166	0	0
T121	1173	8	0	0
T152	2790	13	0	0
T153	1711	4	0	0
T158	1504	14	0	0
T159	1144	8	0	0
T160	2142	5	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1249	0	0
T103	6716	31	0	0
T104	2131	5	0	0
T116	12741	33	0	0
T117	24394	76	0	0
T152	2790	8	0	0
T153	1711	2	0	0
T154	10557	21	0	0
T155	11709	50	0	0
T156	11646	60	0	0
T157	8017	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1288	0	0
T103	6716	29	0	0
T104	2131	2	0	0
T116	12741	36	0	0
T117	24394	85	0	0
T152	2790	11	0	0
T153	1711	3	0	0
T154	10557	12	0	0
T155	11709	64	0	0
T156	11646	44	0	0
T157	8017	15	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1231	0	0
T103	6716	48	0	0
T104	2131	5	0	0
T116	12741	41	0	0
T117	24394	54	0	0
T152	2790	2	0	0
T153	1711	7	0	0
T154	10557	18	0	0
T155	11709	42	0	0
T156	11646	10	0	0
T157	8017	17	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1384	0	0
T103	6716	19	0	0
T116	12741	45	0	0
T117	24394	80	0	0
T152	2790	13	0	0
T153	1711	3	0	0
T154	10557	10	0	0
T155	11709	45	0	0
T156	11646	57	0	0
T157	8017	12	0	0
T161	52265	437	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1342	0	0
T103	6716	30	0	0
T104	2131	6	0	0
T116	12741	22	0	0
T117	24394	67	0	0
T152	2790	16	0	0
T154	10557	24	0	0
T155	11709	47	0	0
T156	11646	47	0	0
T157	8017	10	0	0
T161	52265	458	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T103	6716	27	0	0
T104	2131	4	0	0
T116	12741	36	0	0
T117	24394	79	0	0
T152	2790	2	0	0
T153	1711	4	0	0
T154	10557	33	0	0
T155	11709	73	0	0
T156	11646	71	0	0
T157	8017	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1328	0	0
T103	6716	34	0	0
T116	12741	39	0	0
T117	24394	93	0	0
T152	2790	6	0	0
T153	1711	7	0	0
T154	10557	14	0	0
T155	11709	59	0	0
T156	11646	75	0	0
T157	8017	23	0	0
T161	52265	363	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1340	0	0
T103	6716	36	0	0
T104	2131	5	0	0
T116	12741	52	0	0
T117	24394	110	0	0
T152	2790	8	0	0
T153	1711	1	0	0
T154	10557	19	0	0
T155	11709	63	0	0
T156	11646	29	0	0
T157	8017	16	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1290	0	0
T103	6716	26	0	0
T104	2131	5	0	0
T116	12741	33	0	0
T117	24394	72	0	0
T152	2790	7	0	0
T153	1711	4	0	0
T154	10557	11	0	0
T155	11709	56	0	0
T156	11646	7	0	0
T157	8017	16	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T103	6716	33	0	0
T104	2131	5	0	0
T116	12741	36	0	0
T117	24394	85	0	0
T152	2790	6	0	0
T154	10557	30	0	0
T155	11709	57	0	0
T156	11646	40	0	0
T157	8017	20	0	0
T161	52265	421	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1424	0	0
T103	6716	22	0	0
T104	2131	3	0	0
T116	12741	40	0	0
T117	24394	84	0	0
T152	2790	11	0	0
T153	1711	1	0	0
T154	10557	32	0	0
T155	11709	59	0	0
T156	11646	83	0	0
T157	8017	15	0	0