Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253306542

1

T1

722

T2

276122

T3

22876

full_word

199440413

1

T1

1419

T2

190404

T3

86573

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452746635	1			T1	2141		T2	466526		T3	109449
auto[TlIntgErrCmd]	97	1			T125	4		T126	2		T127	9
auto[TlIntgErrData]	107	1			T125	1		T126	5		T127	2
auto[TlIntgErrBoth]	116	1			T125	5		T126	3		T127	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238899786

1

T1

1113

T2

246003

T3

51399

auto[1]

213847169

1

T1

1028

T2

220523

T3

58050

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	151822035	1			T1	413		T2	166134		T3	17640
auto[TlIntgErrNone]	partial	auto[1]	101484210	1			T1	309		T2	109988		T3	5236
auto[TlIntgErrNone]	full_word	auto[0]	87077613	1			T1	700		T2	79869		T3	33759
auto[TlIntgErrNone]	full_word	auto[1]	112362777	1			T1	719		T2	110535		T3	52814
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T125	2		T126	1		T127	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T125	2		T126	1		T127	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T186	1		T187	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T188	1		T189	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T126	1		T127	2		T180	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T125	1		T126	3		T180	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T180	1		T190	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T126	1		T180	1		T191	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T125	1		T126	2		T127	4
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T125	4		T127	4		T180	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T192	1		T193	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T126	1		T127	1		T186	1