SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.sha3pad_assert_cov_if | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.24 | 96.27 | 93.33 | 100.00 | 100.00 | 93.85 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
ProcessToRun_A | 2147483647 | 348407 | 0 | 0 |
RunThenComplete_M | 2147483647 | 3078571 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 348407 | 0 | 0 |
T1 | 24290 | 9 | 0 | 0 |
T2 | 941433 | 69 | 0 | 0 |
T3 | 341705 | 137 | 0 | 0 |
T13 | 932525 | 246 | 0 | 0 |
T14 | 196642 | 152 | 0 | 0 |
T15 | 325134 | 246 | 0 | 0 |
T16 | 149866 | 80 | 0 | 0 |
T17 | 504123 | 127 | 0 | 0 |
T18 | 125477 | 57 | 0 | 0 |
T19 | 656357 | 324 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 3078571 | 0 | 0 |
T1 | 24290 | 31 | 0 | 0 |
T2 | 941433 | 2701 | 0 | 0 |
T3 | 341705 | 1625 | 0 | 0 |
T13 | 932525 | 5427 | 0 | 0 |
T14 | 196642 | 5767 | 0 | 0 |
T15 | 325134 | 5427 | 0 | 0 |
T16 | 149866 | 204 | 0 | 0 |
T17 | 504123 | 669 | 0 | 0 |
T18 | 125477 | 153 | 0 | 0 |
T19 | 656357 | 6652 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |