Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	96.27	93.33	100.00	100.00	93.85	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	79998	0	0
entropy_period_rd_A	2147483647	2282	0	0
intr_enable_rd_A	2147483647	3460	0	0
prefix_0_rd_A	2147483647	2409	0	0
prefix_10_rd_A	2147483647	2479	0	0
prefix_1_rd_A	2147483647	2374	0	0
prefix_2_rd_A	2147483647	2492	0	0
prefix_3_rd_A	2147483647	2537	0	0
prefix_4_rd_A	2147483647	2521	0	0
prefix_5_rd_A	2147483647	2464	0	0
prefix_6_rd_A	2147483647	2509	0	0
prefix_7_rd_A	2147483647	2523	0	0
prefix_8_rd_A	2147483647	2491	0	0
prefix_9_rd_A	2147483647	2538	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	79998	0	0
T53	576053	76908	0	0
T54	0	61	0	0
T55	0	37	0	0
T122	0	197	0	0
T123	0	183	0	0
T126	0	2	0	0
T129	0	73	0	0
T134	0	2	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	253050	0	0	0
T140	133817	0	0	0
T141	80635	0	0	0
T142	232721	0	0	0
T143	436307	0	0	0
T144	452802	0	0	0
T145	23768	0	0	0
T146	97500	0	0	0
T147	6175	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T102	11694	11	0	0
T104	5632	23	0	0
T106	5165	16	0	0
T138	4339	11	0	0
T155	1594	3	0	0
T156	1649	3	0	0
T157	9688	35	0	0
T158	3256	15	0	0
T159	6723	8	0	0
T160	2527	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3460	0	0
T102	11694	13	0	0
T131	1215	7	0	0
T155	1594	4	0	0
T156	1649	2	0	0
T157	9688	3	0	0
T158	3256	18	0	0
T159	6723	21	0	0
T161	1374	12	0	0
T162	1211	22	0	0
T163	1354	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2409	0	0
T102	11694	13	0	0
T104	5632	20	0	0
T106	5165	14	0	0
T138	4339	12	0	0
T155	1594	5	0	0
T156	1649	1	0	0
T158	3256	6	0	0
T159	6723	7	0	0
T160	2527	8	0	0
T164	10896	54	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2479	0	0
T102	11694	5	0	0
T104	5632	15	0	0
T106	5165	9	0	0
T138	4339	1	0	0
T156	1649	1	0	0
T157	9688	20	0	0
T158	3256	2	0	0
T159	6723	16	0	0
T160	2527	8	0	0
T164	10896	25	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2374	0	0
T102	11694	6	0	0
T104	5632	16	0	0
T106	5165	6	0	0
T138	4339	8	0	0
T155	1594	3	0	0
T156	1649	6	0	0
T157	9688	17	0	0
T158	3256	3	0	0
T159	6723	7	0	0
T160	2527	10	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T102	11694	8	0	0
T104	5632	32	0	0
T106	5165	23	0	0
T138	4339	10	0	0
T155	1594	8	0	0
T157	9688	31	0	0
T158	3256	8	0	0
T159	6723	40	0	0
T160	2527	4	0	0
T164	10896	50	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2537	0	0
T102	11694	16	0	0
T104	5632	21	0	0
T106	5165	21	0	0
T138	4339	13	0	0
T155	1594	5	0	0
T157	9688	12	0	0
T158	3256	7	0	0
T159	6723	1	0	0
T160	2527	2	0	0
T164	10896	51	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T102	11694	16	0	0
T104	5632	27	0	0
T106	5165	6	0	0
T138	4339	8	0	0
T155	1594	6	0	0
T156	1649	3	0	0
T157	9688	34	0	0
T158	3256	13	0	0
T159	6723	3	0	0
T160	2527	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2464	0	0
T102	11694	4	0	0
T104	5632	24	0	0
T106	5165	10	0	0
T126	11643	39	0	0
T138	4339	8	0	0
T157	9688	15	0	0
T158	3256	6	0	0
T159	6723	14	0	0
T160	2527	7	0	0
T164	10896	41	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2509	0	0
T102	11694	7	0	0
T104	5632	22	0	0
T106	5165	9	0	0
T126	11643	55	0	0
T138	4339	2	0	0
T156	1649	5	0	0
T158	3256	11	0	0
T159	6723	33	0	0
T160	2527	12	0	0
T164	10896	64	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2523	0	0
T102	11694	12	0	0
T104	5632	20	0	0
T106	5165	14	0	0
T126	11643	48	0	0
T138	4339	9	0	0
T157	9688	23	0	0
T159	6723	11	0	0
T160	2527	17	0	0
T164	10896	57	0	0
T165	5578	29	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2491	0	0
T102	11694	3	0	0
T104	5632	30	0	0
T106	5165	23	0	0
T138	4339	12	0	0
T155	1594	6	0	0
T157	9688	11	0	0
T158	3256	7	0	0
T159	6723	26	0	0
T160	2527	3	0	0
T164	10896	15	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2538	0	0
T102	11694	15	0	0
T104	5632	18	0	0
T106	5165	23	0	0
T138	4339	6	0	0
T156	1649	3	0	0
T157	9688	22	0	0
T158	3256	5	0	0
T159	6723	9	0	0
T160	2527	15	0	0
T164	10896	55	0	0