Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	253057981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

198328251

1

T1

261202

T2

28707

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	238541615	1			T1	345057		T2	30453		T3	1
values[0x0]	102310070	1			T1	156275		T2	6834		T3	13
values[0x1]	110534547	1			T1	172236		T2	7146		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197355481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

254030751

1

T1

352474

T2

32124

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1308330	1			T1	2572		T2	19		T4	1844
valid_sources[0x01]	1308034	1			T1	2661		T2	10		T4	2000
valid_sources[0x02]	3820357	1			T1	2570		T2	13		T4	1786
valid_sources[0x03]	1436076	1			T1	2607		T2	15		T4	1759
valid_sources[0x04]	1766789	1			T1	2619		T2	12		T4	1785
valid_sources[0x05]	1309814	1			T1	2613		T2	20		T4	1773
valid_sources[0x06]	1444224	1			T1	2601		T2	13		T4	1835
valid_sources[0x07]	1481112	1			T1	2664		T2	12		T4	1888
valid_sources[0x08]	1346485	1			T1	2618		T2	12		T4	1709
valid_sources[0x09]	1308627	1			T1	2587		T2	13		T4	1768
valid_sources[0x0a]	1313676	1			T1	2703		T2	15		T4	1866
valid_sources[0x0b]	1320049	1			T1	2683		T2	14		T4	1761
valid_sources[0x0c]	1405096	1			T1	2662		T2	16		T4	1748
valid_sources[0x0d]	4583124	1			T1	2627		T2	18		T4	1806
valid_sources[0x0e]	1415254	1			T1	2627		T2	16		T4	1903
valid_sources[0x0f]	1305202	1			T1	2569		T2	15		T4	1751
valid_sources[0x10]	1313771	1			T1	2639		T2	18		T4	1721
valid_sources[0x11]	1326766	1			T1	2585		T2	19		T4	1852
valid_sources[0x12]	1765086	1			T1	2662		T2	19		T4	1810
valid_sources[0x13]	1308799	1			T1	2556		T2	11		T4	1791
valid_sources[0x14]	1310683	1			T1	2526		T2	10		T4	1845
valid_sources[0x15]	1432715	1			T1	2593		T2	15		T4	1721
valid_sources[0x16]	1313755	1			T1	2662		T2	11		T4	1786
valid_sources[0x17]	2247338	1			T1	2651		T2	14		T4	1856
valid_sources[0x18]	1308679	1			T1	2598		T2	16		T4	1827
valid_sources[0x19]	1317667	1			T1	2595		T2	7		T4	1778
valid_sources[0x1a]	1329350	1			T1	2651		T2	33		T4	1824
valid_sources[0x1b]	1312289	1			T1	2668		T2	9		T4	1782
valid_sources[0x1c]	1769702	1			T1	2699		T2	10		T4	1757
valid_sources[0x1d]	1317767	1			T1	2589		T2	10		T4	1764
valid_sources[0x1e]	1392628	1			T1	2641		T2	12		T4	1818
valid_sources[0x1f]	1422492	1			T1	2617		T2	11		T4	1874
valid_sources[0x20]	3399742	1			T1	2654		T2	40764		T4	1709
valid_sources[0x21]	1340528	1			T1	2589		T2	23		T4	1736
valid_sources[0x22]	1980060	1			T1	2670		T2	17		T4	1805
valid_sources[0x23]	2210379	1			T1	2677		T2	15		T4	1763
valid_sources[0x24]	1979319	1			T1	2604		T2	13		T4	1782
valid_sources[0x25]	1349118	1			T1	2559		T2	11		T4	1801
valid_sources[0x26]	1314115	1			T1	2708		T2	20		T4	1736
valid_sources[0x27]	1403457	1			T1	2642		T2	15		T4	1613
valid_sources[0x28]	2185110	1			T1	2649		T2	16		T4	1851
valid_sources[0x29]	1313033	1			T1	2546		T2	12		T4	1701
valid_sources[0x2a]	3725995	1			T1	2784		T2	7		T4	1828
valid_sources[0x2b]	1431260	1			T1	2595		T2	21		T4	1769
valid_sources[0x2c]	1316616	1			T1	2658		T2	16		T4	1750
valid_sources[0x2d]	1311106	1			T1	2659		T2	19		T4	1743
valid_sources[0x2e]	1308649	1			T1	2618		T2	14		T4	1829
valid_sources[0x2f]	1305874	1			T1	2610		T2	17		T4	1650
valid_sources[0x30]	1319650	1			T1	2579		T2	18		T4	1715
valid_sources[0x31]	1307930	1			T1	2565		T2	10		T4	1922
valid_sources[0x32]	1965672	1			T1	2663		T2	13		T4	1765
valid_sources[0x33]	1771588	1			T1	2687		T2	20		T4	2006
valid_sources[0x34]	1315502	1			T1	2645		T2	11		T4	1859
valid_sources[0x35]	1457999	1			T1	2639		T2	16		T4	1713
valid_sources[0x36]	1315686	1			T1	2598		T2	18		T4	1577
valid_sources[0x37]	1342470	1			T1	2632		T2	14		T4	1845
valid_sources[0x38]	4053304	1			T1	2650		T2	22		T4	1728
valid_sources[0x39]	2366380	1			T1	2614		T2	21		T4	1820
valid_sources[0x3a]	3749714	1			T1	2634		T2	17		T4	1877
valid_sources[0x3b]	1310457	1			T1	2618		T2	25		T4	1808
valid_sources[0x3c]	1333278	1			T1	2549		T2	18		T4	1952
valid_sources[0x3d]	1304562	1			T1	2663		T2	16		T4	1749
valid_sources[0x3e]	1358235	1			T1	2636		T2	13		T4	1839
valid_sources[0x3f]	1312588	1			T1	2542		T2	15		T4	1692
valid_sources[0x40]	2219530	1			T1	2597		T2	13		T4	1885
valid_sources[0x41]	5683931	1			T1	2630		T2	12		T4	1805
valid_sources[0x42]	2279420	1			T1	2525		T2	13		T4	1756
valid_sources[0x43]	2269123	1			T1	2616		T2	12		T4	1859
valid_sources[0x44]	3752708	1			T1	2707		T2	17		T4	1872
valid_sources[0x45]	2233360	1			T1	2616		T2	8		T4	1827
valid_sources[0x46]	1312848	1			T1	2694		T2	8		T4	1881
valid_sources[0x47]	1302710	1			T1	2653		T2	17		T4	1747
valid_sources[0x48]	1307225	1			T1	2640		T2	19		T4	1810
valid_sources[0x49]	1307102	1			T1	2582		T2	11		T4	1695
valid_sources[0x4a]	1312101	1			T1	2589		T2	14		T4	1678
valid_sources[0x4b]	1431323	1			T1	2572		T2	11		T4	1824
valid_sources[0x4c]	1317490	1			T1	2623		T2	16		T4	1724
valid_sources[0x4d]	1303876	1			T1	2741		T2	11		T4	1948
valid_sources[0x4e]	1768996	1			T1	2669		T2	15		T4	1743
valid_sources[0x4f]	1310732	1			T1	2632		T2	12		T4	1791
valid_sources[0x50]	1310662	1			T1	2589		T2	16		T4	1970
valid_sources[0x51]	1315165	1			T1	2606		T2	12		T4	1730
valid_sources[0x52]	1313821	1			T1	2704		T2	17		T4	1710
valid_sources[0x53]	2216647	1			T1	2699		T2	17		T4	1788
valid_sources[0x54]	1453124	1			T1	2504		T2	14		T4	1888
valid_sources[0x55]	1974072	1			T1	2631		T2	11		T4	1746
valid_sources[0x56]	1314052	1			T1	2706		T2	16		T4	1774
valid_sources[0x57]	4381238	1			T1	2651		T2	11		T4	1634
valid_sources[0x58]	1303302	1			T1	2672		T2	20		T4	1778
valid_sources[0x59]	2218758	1			T1	2591		T2	11		T4	1731
valid_sources[0x5a]	2249785	1			T1	2649		T2	15		T4	1891
valid_sources[0x5b]	1307848	1			T1	2511		T2	21		T4	1860
valid_sources[0x5c]	1309637	1			T1	2695		T2	12		T4	1755
valid_sources[0x5d]	2177394	1			T1	2676		T2	22		T4	1916
valid_sources[0x5e]	2194367	1			T1	2709		T2	19		T4	1862
valid_sources[0x5f]	1313614	1			T1	2585		T2	13		T4	1829
valid_sources[0x60]	1758468	1			T1	2592		T2	10		T4	1830
valid_sources[0x61]	1308649	1			T1	2628		T2	21		T4	1854
valid_sources[0x62]	1309065	1			T1	2551		T2	14		T4	1828
valid_sources[0x63]	1305673	1			T1	2606		T2	11		T4	1788
valid_sources[0x64]	1692976	1			T1	2634		T2	7		T4	1723
valid_sources[0x65]	1318735	1			T1	2721		T2	16		T4	1726
valid_sources[0x66]	1301480	1			T1	2649		T2	9		T4	1650
valid_sources[0x67]	1386407	1			T1	2573		T2	20		T4	1694
valid_sources[0x68]	2332394	1			T1	2683		T2	21		T4	1695
valid_sources[0x69]	1311392	1			T1	2649		T2	8		T4	1742
valid_sources[0x6a]	1796100	1			T1	2653		T2	11		T4	1797
valid_sources[0x6b]	1311174	1			T1	2616		T2	16		T4	1722
valid_sources[0x6c]	1977701	1			T1	2627		T2	20		T4	1766
valid_sources[0x6d]	3349699	1			T1	2597		T2	15		T4	1710
valid_sources[0x6e]	3344521	1			T1	2642		T2	9		T4	1843
valid_sources[0x6f]	1310759	1			T1	2719		T2	11		T4	1817
valid_sources[0x70]	2851830	1			T1	2759		T2	12		T4	1877
valid_sources[0x71]	1342231	1			T1	2629		T2	15		T4	1913
valid_sources[0x72]	1618034	1			T1	2564		T2	12		T4	1731
valid_sources[0x73]	1313101	1			T1	2676		T2	8		T4	1831
valid_sources[0x74]	3722169	1			T1	2678		T2	11		T4	1750
valid_sources[0x75]	1310512	1			T1	2674		T2	12		T4	1918
valid_sources[0x76]	1298992	1			T1	2658		T2	21		T4	1945
valid_sources[0x77]	1307119	1			T1	2655		T2	11		T4	1665
valid_sources[0x78]	3055367	1			T1	2586		T2	11		T4	1796
valid_sources[0x79]	1450114	1			T1	2667		T2	17		T4	1797
valid_sources[0x7a]	2361530	1			T1	2733		T2	12		T4	1863
valid_sources[0x7b]	1974386	1			T1	2669		T2	23		T4	1772
valid_sources[0x7c]	1304244	1			T1	2584		T2	17		T4	1724
valid_sources[0x7d]	3374896	1			T1	2593		T2	11		T4	1767
valid_sources[0x7e]	5400395	1			T1	2674		T2	12		T4	1882
valid_sources[0x7f]	1309178	1			T1	2723		T2	13		T4	1851
valid_sources[0x80]	1331992	1			T1	2647		T2	12		T4	1877

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86647920

1

T1

100772

T2

20895

T4

71597

values[0x0]

all_enables

biggest_size

60101379

1

T1

86702

T2

4211

T3

5

values[0x1]

all_enables

biggest_size

51578952

1

T1

73728

T2

3601

T3

3